MT48LC16M16A2TG75ITTR Micron Technology Inc, MT48LC16M16A2TG75ITTR Datasheet - Page 85
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MT48LC16M16A2TG75ITTR
Manufacturer Part Number
MT48LC16M16A2TG75ITTR
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC16M16A2TG75ITTR.pdf
(92 pages)
Specifications of MT48LC16M16A2TG75ITTR
Organization
16Mx16
Density
256Mb
Address Bus
15b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
135mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Not Compliant
Power-Down
Figure 53: Power-Down Mode
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Command
BA0, BA1
Address
Precharge all
active banks
DQM
CKE
CLK
A10
DQ
High-Z
t CMS
t CKS
PRECHARGE
t AS
Single bank
All banks
Bank(s)
T0
t CMH
t CKH
t AH
Note:
Two clock cycles
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND IN-
HIBIT when no accesses are in progress. If power-down occurs when all banks are idle,
this mode is referred to as precharge power-down; if power-down occurs when there is
a row active in any bank, this mode is referred to as active power-down. Entering power-
down deactivates the input and output buffers, excluding CKE, for maximum power
savings while in standby. The device cannot remain in the power-down state longer
than the refresh period (64ms) because no REFRESH operations are performed in this
mode.
The power-down state is exited by registering a NOP or COMMAND INHIBIT with CKE
HIGH at the desired clock edge (meeting
All banks idle, enter
power-down mode
t CK
1. Violating refresh requirements during power-down may result in a loss of data.
T1
NOP
t CL
t CKS
T2
NOP
t CH
Input buffers gated off
while in power-down mode
85
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Exit power-down mode
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
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t
CKS).
256Mb: x4, x8, x16 SDRAM
t CKS
Tn + 1
NOP
All banks idle
© 1999 Micron Technology, Inc. All rights reserved.
Tn + 2
Power-Down
ACTIVE
Row
Bank
Row
Don’t Care