MT48LC64M4A2TG-7E:D TR Micron Technology Inc, MT48LC64M4A2TG-7E:D TR Datasheet - Page 75
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MT48LC64M4A2TG-7E:D TR
Manufacturer Part Number
MT48LC64M4A2TG-7E:D TR
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC64M4A2TG-7ED_TR.pdf
(87 pages)
Specifications of MT48LC64M4A2TG-7E:D TR
Organization
64Mx4
Density
256Mb
Address Bus
15b
Access Time (max)
5.4ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
135mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Not Compliant
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Figure 45: WRITE With Auto Precharge Interrupted by a READ
Figure 46: WRITE With Auto Precharge Interrupted by a WRITE
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Internal
States
Internal
States
Command
Command
Note:
Note:
Address
Address
Bank m
Bank m
Bank n
Bank n
CLK
CLK
DQ
DQ
1. DQM is LOW.
1. DQM is LOW.
Page active
Page active
NOP
T0
T0
NOP
WRITE - AP
WRITE - AP
Page active
Bank n,
Page active
Bank n,
Bank n
Bank n
Col a
T1
D
T1
Col a
D
IN
IN
WRITE with burst of 4
WRITE with burst of 4
T2
T2
NOP
D
NOP
D
IN
IN
75
READ - AP
Bank m,
T3
T3
Col d
Bank m
D
NOP
IN
Interrupt burst, write-back
t
WR - bank n
READ with burst of 4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
WRITE - AP
Bank m,
Col d
T4
Bank m
T4
D
NOP
CL = 3 (bank m)
t
Interrupt burst, write-back
WR - bank n
IN
WRITE with burst of 4
T5
T5
NOP
NOP
D
256Mb: x4, x8, x16 SDRAM
t
IN
Precharge
RP - bank n
PRECHARGE Operation
T6
T6
NOP
D
NOP
D
OUT
t RP - bank n
Precharge
IN
© 1999 Micron Technology, Inc. All rights reserved.
Don’t Care
Don’t Care
T7
T7
D
NOP
NOP
D
t WR - bank m
OUT
t RP - bank m
IN
Write-back
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