MT48LC64M4A2TG-7E:D TR Micron Technology Inc, MT48LC64M4A2TG-7E:D TR Datasheet - Page 56
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MT48LC64M4A2TG-7E:D TR
Manufacturer Part Number
MT48LC64M4A2TG-7E:D TR
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC64M4A2TG-7ED_TR.pdf
(87 pages)
Specifications of MT48LC64M4A2TG-7E:D TR
Organization
64Mx4
Density
256Mb
Address Bus
15b
Access Time (max)
5.4ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
135mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Not Compliant
- Current page: 56 of 87
- Download datasheet (4Mb)
Figure 26: Terminating a READ Burst
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Note:
Continuous-page READ bursts can be truncated with a BURST TERMINATE command
and fixed-length READ bursts can be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at which the last desired data element is
valid, where x = CL - 1. This is shown in Figure 26 (page 56) for each possible CAS
latency; data element n + 3 is the last desired data element of a longer burst.
Command
Command
1. DQM is LOW.
Address
Address
CLK
CLK
DQ
DQ
Bank,
T0
Col n
T0
READ
Bank,
READ
Col n
CL = 2
CL = 3
T1
T1
NOP
NOP
56
T2
T2
NOP
NOP
D
OUT
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T3
T3
NOP
NOP
D
D
OUT
OUT
TERMINATE
TERMINATE
BURST
BURST
T4
T4
X = 1 cycle
D
D
256Mb: x4, x8, x16 SDRAM
OUT
OUT
Transitioning data
X = 2 cycles
T5
T5
NOP
NOP
D
D
OUT
OUT
© 1999 Micron Technology, Inc. All rights reserved.
T6
T6
READ Operation
NOP
NOP
D
OUT
Don’t Care
T7
NOP
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