MT47H128M16RT-25E:C Micron Technology Inc, MT47H128M16RT-25E:C Datasheet - Page 29

• Manufacturer Part Number: MT47H128M16RT-25E:C
• Description: DRAM Chip DDR2 SDRAM 2G-Bit 128Mx16 1.8V 84-Pin FBGA Tray
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr
• Series: -r

Specifications of MT47H128M16RT-25E:C

• Package: 84FBGA
• Density: 2 Gb
• Address Bus Width: 17 Bit
• Operating Supply Voltage: 1.8 V
• Maximum Clock Rate: 800 MHz
• Maximum Random Access Time: 0.4 ns
• Operating Temperature: 0 to 70 °C
• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 2G (128M x 16)
• Speed: 2.5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Package / Case: 84-TFBGA
• Lead Free Status / RoHS Status: Compliant

Table 10: DDR2 I
Notes 1–7 apply to the entire table
PDF: 09005aef824f87b6
2gbddr2.pdf – Rev. E 06/10 EN
Parameter/Condition
Operating one bank active-precharge current:
t
CKE is HIGH, CS# is HIGH between valid commands; Ad-
dress bus inputs are switching; Data bus inputs are
switching
Operating one bank active-read-precharge cur-
rent:
Iout = 0mA; BL = 4, CL = CL (I
t
CKE is HIGH, CS# is HIGH between valid commands; Ad-
dress bus inputs are switching; Data pattern is same as
I
Precharge power-down current: All banks idle;
=
inputs are stable; Data bus inputs are floating
Precharge quiet standby current: All banks idle;
=
address bus inputs are stable; Data bus inputs are float-
ing
Precharge standby current: All banks idle;
(I
dress bus inputs are switching; Data bus inputs are
switching
Active power-down current: All banks open;
t
inputs are stable; Data bus inputs are floating
Active standby current: All banks open;
(I
HIGH, CS# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus
inputs are switching
Operating burst write current: All banks open, con-
tinuous burst writes; BL = 4, CL = CL (I
t
HIGH, CS# is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switching
Operating burst read current: All banks open, con-
tinuous burst reads, I
AL = 0;
(I
mands; Address bus inputs are switching; Data bus in-
puts are switching
CK =
RC =
DD4W
CK (I
CK (I
DD
DD
DD
t
t
CK (I
CK (I
); CKE is HIGH, CS# is HIGH; Other control and ad-
),
); CKE is HIGH, CS# is HIGH between valid com-
DD
DD
t
t
t
RAS =
RC (I
CK (I
DD
DD
); CKE is LOW; Other control and address bus
),
t
CK =
); CKE is LOW; Other control and address bus
); CKE is HIGH, CS# is HIGH; Other control and
t
RAS =
DD
DD
t
),
RAS MAX (I
t
),
CK (I
t
t
RAS =
RC =
t
RAS MAX (I
DD
DD
OUT
),
t
RC (I
t
RAS MIN (I
t
Specifications and Conditions (Die Revision A)
RAS =
DD
= 0mA; BL = 4, CL = CL (I
DD
),
),
DD
DD
t
RP =
t
t
RAS MAX (I
),
RAS =
), AL = 0;
t
DD
RP =
t
RP (I
),
t
t
DD
RAS MIN (I
RCD =
t
RP (I
DD
), AL = 0;
t
CK =
); CKE is
DD
t
CK =
DD
),
t
t
RCD (I
); CKE is
CK =
t
t
RP =
CK (I
t
CK =
t
DD
DD
CK
t
CK =
t
);
t
CK
),
DD
DD
t
t
CK
RP
CK
),
);
Symbol
I
I
I
I
I
I
I
I
DD3Pf
DD3Ps
DD4W
I
I
DD2Q
DD2N
DD3N
DD2P
DD4R
29
DD0
DD1
Electrical Specifications – I
Configuration
Slow PDN exit
Fast PDN exit
Micron Technology, Inc. reserves the right to change products or specifications without notice.
MR[12] = 0
MR[12] = 1
x4, x8, x16
x4, x8
x4, x8
x4, x8
x4, x8
x4, x8
x4, x8
x4, x8
x16
x16
x16
x16
x16
x16
x16
2Gb: x4, x8, x16 DDR2 SDRAM
115
150
165
180
180
270
190
295
-25
12
65
75
70
80
45
14
65
85
-3E/-3 -37E
100
135
145
160
160
250
170
275
12
55
65
60
70
40
14
55
75
© 2006 Micron Technology, Inc. All rights reserved.
115
105
135
130
190
150
195
DD
90
12
45
45
50
60
35
14
45
55
Parameters
115
105
135
125
160
140
180
-5E
90
12
40
40
45
50
30
14
40
50
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA