MT41J128M16HA-187E:D Micron Technology Inc, MT41J128M16HA-187E:D Datasheet - Page 168
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MT41J128M16HA-187E:D
Manufacturer Part Number
MT41J128M16HA-187E:D
Description
IC DDR3 SDRAM 2GBIT 96FBGA
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Series
-r
Specifications of MT41J128M16HA-187E:D
Organization
128Mx16
Density
1Gb
Address Bus
17b
Maximum Clock Rate
1.066GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
210mA
Pin Count
96
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
2G (128M x 16)
Speed
533MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
96-TFBGA
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT41J128M16HA-187E:D
Manufacturer:
Micron
Quantity:
1 602
Company:
Part Number:
MT41J128M16HA-187E:D
Manufacturer:
Micron Technology Inc
Quantity:
10 000
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Figure 84: WRITE Burst
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
Command 1
DQS, DQS#
DQS, DQS#
DQS, DQS#
Address 2
DQ 3
DQ 3
DQ 3
CK#
CK
t DQSS (NOM)
t DQSS (MAX)
t DQSS (MIN)
WRITE
Bank,
Col n
T0
NOP
T1
Notes:
WL = AL + CWL
1. NOP commands are shown for ease of illustration; other commands may be valid at
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
3. DI n = data-in for column n.
4. BL8, WL = 5 (AL = 0, CWL = 5).
5.
6.
NOP
T2
these times.
the WRITE command at T0.
t
t
ly ends when DQS no longer drives LOW and DQS# no longer drives HIGH.
DQSS must be met at each rising clock edge.
WPST is usually depicted as ending at the crossing of DQS, DQS#; however,
NOP
T3
t DQSH
NOP
T4
t DQSH
t WPRE
t DQSH
t WPRE
t DQSL
168
t DQSL
t WPRE
t DQSS t DSH
t DSS
DI
n
t DSS
t DQSH
t DQSL
NOP
DI
T5
n
t DQSS
t DQSH
t DSH
n + 1
DI
DI
n
t DQSH
t DQSL
n + 1
DI
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t DQSL
t DSS
n + 2
n + 1
DI
DI
t DSS
t DQSH
t DQSL
NOP
n + 2
T6
DI
t DSH
t DQSH
t DSH
n + 3
n + 2
DI
DI
t DQSH
t DQSL
2Gb: x4, x8, x16 DDR3 SDRAM
n + 3
DI
t DQSL
n + 4
t DSS
n + 3
DI
DI
t DSS
t DQSH
t DQSL
n + 4
NOP
T7
DI
t DSH
t DQSH
t DSH
n + 4
n + 5
DI
DI
t DQSH
t DQSL
n + 5
DI
t DQSL
t DSS
n + 6
n + 5
DI
DI
t DSS
t DQSH
t DQSL
n + 6
NOP
© 2006 Micron Technology, Inc. All rights reserved.
T8
DI
t DSH
t DQSH
t DSH
n + 7
n + 6
DI
DI
WRITE Operation
t DQSH
t WPST
t DQSL
n + 7
Transitioning Data
DI
t DQSL
t WPST
t DSS
n + 7
DI
t DSS
t WPST
t DQSL
NOP
T9
t
WPST actual-
Don’t Care
T10
NOP
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