MT41J128M16HA-187E:D Micron Technology Inc, MT41J128M16HA-187E:D Datasheet - Page 14
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MT41J128M16HA-187E:D
Manufacturer Part Number
MT41J128M16HA-187E:D
Description
IC DDR3 SDRAM 2GBIT 96FBGA
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Series
-r
Specifications of MT41J128M16HA-187E:D
Organization
128Mx16
Density
1Gb
Address Bus
17b
Maximum Clock Rate
1.066GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
210mA
Pin Count
96
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
2G (128M x 16)
Speed
533MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
96-TFBGA
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT41J128M16HA-187E:D
Manufacturer:
Micron
Quantity:
1 602
Company:
Part Number:
MT41J128M16HA-187E:D
Manufacturer:
Micron Technology Inc
Quantity:
10 000
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Functional Block Diagrams
Figure 3: 512 Meg x 4 Functional Block Diagram
RZQ
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
V
SSQ
A[14:0]
BA[2:0]
ZQ
CK, CK#
RESET#
RAS#
CAS#
WE#
ODT
CKE
A12
CS#
18
Address
register
Mode registers
Control
logic
18
15
counter
Refresh
ZQCL, ZQCS
11
3
BC4 (burst chop)
OTF
DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally
configured as an 8-bank DRAM.
15
address
3
Row-
MUX
Column-
counter/
control
address
15
Bank
logic
latch
ZQ CAL
decoder
address
Bank 0
row-
latch
and
Bank 1
Bank 2
8
3
Bank 3
Bank 4
32,768
Bank 5
Bank 6
Columns 0, 1, and 2
Bank 7
To pullup/pulldown
(32,768 x 256 x 32)
Sense amplifiers
DM mask logic
I/O gating
Column
decoder
networks
memory
Bank 0
(x32)
8,192
array
256
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
14
Bank 7
DM
32
BC4
OTF
Micron Technology, Inc. reserves the right to change products or specifications without notice.
32
32
Columns 0, 1, and 2
interface
READ
CK,CK#
FIFO
data
MUX
and
Data
2Gb: x4, x8, x16 DDR3 SDRAM
Data
4
4
lower nibble for BC4)
(select upper or
Functional Block Diagrams
Column 2
WRITE
drivers
input
and
logic
control
ODT
CK,CK#
drivers
READ
DLL
BC4
© 2006 Micron Technology, Inc. All rights reserved.
DQS, DQS#
sw1
sw1
sw1
DQ[3:0]
R
V
V
R
V
R
TT,nom
DDQ
TT,nom
DDQ
DDQ
TT,nom
/2
/2
/2
sw2
R
R
sw2
sw2
R
TT(WR)
TT(WR)
TT(WR)
(1, 2)
(1 . . . 4)
DQ[3:0]
DQS, DQS#
DM
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