MT29C4G48MAPLCJI-6 IT TR Micron Technology Inc, MT29C4G48MAPLCJI-6 IT TR Datasheet - Page 8

• Manufacturer Part Number: MT29C4G48MAPLCJI-6 IT TR
• Manufacturer: Micron Technology Inc

Specifications of MT29C4G48MAPLCJI-6 IT TR

• Operating Supply Voltage (max): 1.95V
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

PDF: 09005aef83070ff3
168ball_nand_lpdram_j4xx_omap.pdf - Rev. I 6/09
Note:
Table 3: x16, x32 LPDDR Ball Descriptions
UDQS, LDQS (x16)
UDM, LDM (x16)
1. Balls marked RFU may or may not be connected internally. These balls should not be
DQ[15:0] (x16)
DQ[31:0] (x32)
DQS[3:0] (x32)
DM[3:0] (x32)
A[14:0] (x16)
A[14:0] (x32)
CKE0, CKE1
CS0#, CS1#
used. Contact factory for details.
BA0, BA1
Symbol
CK, CK#
Vddq
CAS#
RAS#
WE#
Vssq
Vdd
TQ
168-Ball NAND Flash and LPDRAM PoP (TI OMAP) MCP
Output Temperature sensor output: TQ HIGH when LPDDR T
output
output
Supply
Supply
Supply
Input/
Input/
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Address inputs: Specifies the row or column address. Also
used to load the mode registers. The maximum LPDDR ad-
dress is determined by density and configuration. Consult the
LPDDR product data sheet for the maximum address for a giv-
en density and configuration. Unused address balls
become RFU.
Bank address inputs: Specifies one of the 4 banks.
Column select: Specifies which command to execute.
CK is the system clock. CK and CK# are differential clock
inputs. All address and control signals are sampled and
referenced on the crossing of the rising edge of CK with the
falling edge of CK#.
Clock enable.
CKE0 is used for a single LPDDR product.
CKE1 is used for dual LPDDR products and is considered RFU
for single LPDDR MCPs.
Chip select:
CS0# is used for a single LPDDR product.
CS1# is used for dual LPDDR products and is considered RFU
for single LPDDR MCPs.
Data mask: Determines which bytes are written
during WRITE operations.
For x16 LPDDR, unused DM balls become RFU.
Row select: Specifies the command to execute.
Write enable: Specifies the command to execute.
Data bus: Data inputs/outputs.
DQ[31:16] are RFU for x16 LPDDR devices.
Data strobe: Coordinates READ/WRITE transfers of data; one
DQS per DQ byte.
For x16 LPDDR, unused DQS balls become RFU.
exceeds 85°C.
Vdd: LPDDR power supply.
Vddq: LPDDR I/O power supply.
Vssq: LPDDR I/O ground.
8
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Ball Assignments and Descriptions
1
Description
©2007 Micron Technology, Inc. All rights reserved.
J