LRS1392A Sharp Electronics, LRS1392A Datasheet - Page 8

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LRS1392A

Manufacturer Part Number
LRS1392A
Description
Manufacturer
Sharp Electronics
Datasheet

Specifications of LRS1392A

Lead Free Status / RoHS Status
Supplier Unconfirmed
sharp
3. Truth Table
3.1 Bus Operation
Notes:
Reset Power
Down
Read
Output
Disable
Write
Standby
Standby
Reset Power
Down
1. L = V
2. Command writes involving block erase, (page buffer) program or OTP program are reliably executed when F-V
3. Never hold F-OE low and F-WE low at the same timing.
4. Refer Section 5. Command Definitions for Flash Memory valid D
5. F-WP set to V
6. Electricity consumption of Flash Memory is lowest when F-RST = GND ±0.2V.
7. Flash Read Mode
8. SRAM Standby Mode
Read Array
Read Identifier Codes/OTP
Read Query
S-CE
Flash
H
X
X
V
Command writes involving full chip erase is reliably executed when F-V
Block erase, full chip erase, (page buffer) program or OTP program with F-V
results and should not be attempted.
PPH1/2
1
S-CE
IL
, H = V
X
X
Standby
Read
Output
Disable
Write
Read
Output
Disable
Write
Standby
L
SRAM Notes
and F-V
2
Mode
(1)
IL
S-LB
IH
X
X
H
or V
CC
, X = H or L, High-Z = High impedance. Refer to the DC Characteristics.
2,3,4,5
3,5
5,6
5,6
5,6
5,6
= 2.7V to 3.3V.
5
5
5
5
5
IH
S-UB
.
X
X
H
F-CE
H
X
H
X
L
Refer to the Appendix
F-RST F-OE F-WE S-CE
H
H
H
L
L
Address
See 5.2
9. S-UB, S-LB Control Mode
S-LB
X
H
X
X
X
L
H
L
L
L R S 1 3 9 2 A
S-UB
H
X
X
X
L
H
L
L
DQ
L
L
D
D
High-Z
OUT
OUT
IN
1
(8)
(8)
Refer to the Appendix
0
to DQ
S-CE
during a write operation.
/D
/D
H
H
DQ
IN
IN
2
See 5.2
0
7
PP
D
to DQ
OUT
S-OE S-WE S-LB S-UB DQ
= V
DQ
X
H
X
X
H
X
X
X
L
L
D
D
High-Z
OUT
OUT
PPH1
8
15
PP
to DQ
/D
/D
< V
X
H
H
X
L
H
H
X
L
X
and F-V
IN
IN
15
PPH1/2
X
H
X
H
CC
(8)
(8)
(Min.) produce spurious
= 2.7V to 3.3V.
X
H
X
H
(9)
(9)
(9)
(9)
High-Z
High-Z
High-Z
High-Z
0
D
to DQ
(7)
IN
PP
15
=
5

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