PF38F3050M0Y0CFA Micron Technology Inc, PF38F3050M0Y0CFA Datasheet - Page 83
PF38F3050M0Y0CFA
Manufacturer Part Number
PF38F3050M0Y0CFA
Description
Manufacturer
Micron Technology Inc
Datasheet
1.PF38F3050M0Y0CFA.pdf
(102 pages)
Specifications of PF38F3050M0Y0CFA
Operating Supply Voltage (max)
1.95V
Operating Temperature (max)
85C
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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Numonyx™ Wireless Flash Memory (W18)
Figure 39: Data Output Configuration with WAIT Signal Delay
Note:
14.6
14.7
November 2007
Order Number: 290701-18
Data Hold
Data Hold
1 CLK
2 CLK
WAIT shown asserted high (RCR[10]=1).
WAIT (CR.8 = 1)
WAIT (CR.8 = 0)
WAIT (CR.8 = 1)
WAIT (CR.8 = 0)
DQ
DQ
WAIT Delay (RCR[8])
The WAIT configuration bit (RCR[8]) controls WAIT signal delay behavior for all
synchronous read-array modes. Its setting depends on the system and CPU
characteristics. The WAIT can be asserted either during, or one data cycle before, a
valid output.
In synchronous linear read array (no-wrap mode RCR[3]=1) of 4-, 8-, 16-, or
continuous-word burst mode, an output delay may occur when a burst sequence
crosses its first device-row boundary (16-word boundary). If the burst start address is
4-word boundary aligned, the delay does not occur. If the start address is misaligned to
a 4-word boundary, the delay occurs once per burst-mode read sequence. The WAIT
signal informs the system of this delay.
Burst Sequence (RCR[7])
The burst sequence specifies the synchronous-burst mode data order (see
“Sequence and Burst Length” on page
either 4-, 8-, or 16-word burst length with the burst wrap bit (RCR[3]) set, or in
continuous burst mode, the device may incur an output delay when the burst sequence
crosses the first 16-word boundary. (See
word boundary description.) This depends on the starting address. If the starting
address is aligned to a 4-word boundary, there is no delay. If the starting address is the
end of a 4-word boundary, the output delay is one clock cycle less than the First Access
Latency Count; this is the worst-case delay. The delay takes place only once, and only
if the burst sequence crosses a 16-word boundary. The WAIT pin informs the system of
this delay. For timing diagrams of WAIT functionality, see these figures:
CLK [C]
•
•
•
15-0
15-0
Figure 9, “Single Synchronous Read-Array Operation Waveform” on page 32
Figure 10, “Synchronous 4-Word Burst Read Operation Waveform” on page 33
Figure 11, “WAIT Functionality for EOWL (End-of-Word Line) Condition Waveform”
on page 34
[Q]
[Q]
t
CHTL/H
84). When operating in a linear burst mode,
Figure 37, “Word Boundary” on page 80
t
t
CHQV
CHQV
Output
Valid
Output
Valid
Note 1
Note 1
Note 1
Note 1
Output
Valid
Output
Valid
Table 35,
Output
Valid
Datasheet
for
83
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