PF38F3050M0Y0CFA Micron Technology Inc, PF38F3050M0Y0CFA Datasheet - Page 48
PF38F3050M0Y0CFA
Manufacturer Part Number
PF38F3050M0Y0CFA
Description
Manufacturer
Micron Technology Inc
Datasheet
1.PF38F3050M0Y0CFA.pdf
(102 pages)
Specifications of PF38F3050M0Y0CFA
Operating Supply Voltage (max)
1.95V
Operating Temperature (max)
85C
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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9.0
9.1
Table 21: Bus Operations Summary
9.1.1
Datasheet
48
Read
Write
Output Disable
Standby
Reset
Notes:
1.
2.
3.
4.
Bus Operation
WAIT is only valid during synchronous array-read operations.
Refer to the
operation.
X = Don’t Care (H or L).
RST# must be at V
Asynchronous
Synchronous
Burst Suspend
Bus Operations Overview
This section provides an overview of device bus operations. The Numonyx™ Wireless
Flash Memory (W18) family includes an on-chip WSM to manage block erase and
program algorithms. Its Command User Interface (CUI) allows minimal processor
overhead with RAM-like interface timings. Device commands are written to the CUI
using standard microprocessor timings.
Bus Operations
Bus cycles to/from the W18 device conform to standard microprocessor bus operations.
Table 21
the device’s control signal inputs.
Reads
Device read operations are performed by placing the desired address on A[22:0] and
asserting CE# and OE#. ADV# must be low, and WE# and RST# must be high. All read
operations are independent of the voltage level on V
CE#-low selects the device and enables its internal circuits. OE#-low or WE#-low
determine whether DQ[15:0] are outputs or inputs, respectively. OE# and WE# must
not be low at the same time - indeterminate device operation will result.
In asynchronous-page mode, the rising edge of ADV# can be used to latch the address.
If only asynchronous read mode is used, ADV# can be tied to ground. CLK is not used
in asynchronous-page mode and should be tied high.
In synchronous-burst mode, ADV# is used to latch the initial address - either on the
rising edge of ADV# or the rising (or falling) edge of CLK with ADV# low, whichever
occurs first. CLK is used in synchronous-burst mode to increment the internal address
counter, and to output read data on DQ[15:0].
Each device partition can be placed in any of several read states:
• Read Array: Returns flash array data from the addressed location.
• Read Identifier (ID): Returns manufacturer ID and device ID codes, block lock
Table 23, “Bus Cycle Definitions” on page 52
status, and protection register data. Read Identifier information can be accessed
from any 4-Mbit partition base address.
SS
summarizes the bus operations and the logic levels that must be applied to
RST#
± 0.2 V to meet the maximum specified power-down current.
V
V
V
V
V
V
V
IH
IH
IH
IH
IH
IH
IL
Running
Halted
CLK
X
X
X
X
X
ADV#
X
X
X
X
L
L
L
CE#
H
X
L
L
L
L
L
OE#
H
H
H
L
X
X
L
for valid DQ[15:0] during a write
Numonyx™ Wireless Flash Memory (W18)
Numonyx™ Wireless Flash Memory (W18)
PP
WE#
.
H
H
H
H
L
X
X
Asserted
Asserted
Asserted
High-Z
High-Z
Driven
WAIT
Active
Order Number: 290701-18
DQ[15:0
Output
Output
Output
High-Z
High-Z
High-Z
Input
]
November 2007
Notes
3,4
1
2
3
3
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