LM1237BDKD/NA/NOPB National Semiconductor, LM1237BDKD/NA/NOPB Datasheet - Page 36

• Manufacturer Part Number: LM1237BDKD/NA/NOPB
• Manufacturer: National Semiconductor

Specifications of LM1237BDKD/NA/NOPB

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Package Type: MDIP
• Lead Free Status / RoHS Status: Compliant

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Control Register Definitions
Pre-Amplifier Interface Registers
BLUE CHANNEL GAIN REGISTER
Register Name (address): BGAINCTRL (0x8430)
GREEN CHANNEL GAIN REGISTER
Register Name (address): GGAINCTRL (0x8431)
RED CHANNEL GAIN REGISTER
Register Name (address): RGAINCTRL (0x8432)
CONTRAST CONTROL REGISTER
Register Name (address): CONTRCTRL (0x8433)
DAC 1 REGISTER
Register Name (address): DAC1CTRL (0x8434)
DAC 2 REGISTER
Register Name (address): DAC2CTRL (0x8435)
Bits 31–0
Bits 6–0
Bit 7
Bits 6–0
Bit 7
Bits 6–0
Bit 7
Bits 6–0
Bit 7
Bits 7–0
RSV
RSV
RSV
RSV
GC7
BC7
7
7
7
7
7
7
These are the Display Window 2 Column Width 2x Enable Bits. These thirty-two bits correspond to columns
31–0 of Display Window 2, respectively. A value of zero indicates the column will have normal width (12 OSD
pixels). A value of one indicates the column will be twice as wide as normal (24 OSD pixels). For the double
wide case, each Character Font pixel location will be displayed twice, in two consecutive horizontal pixel
locations. The user should note that if more than 32 display characters are programmed to reside on a row,
then all display characters after the first thirty-two will have normal width (12 pixels).
This register determines the gain of the blue video channel.
Reserved and should be set to zero.
This register determines the gain of the green video channel.
Reserved and should be set to zero.
This register determines the gain of the red video channel.
Reserved and should be set to zero.
This register determines the contrast gain and affects all three channels, blue, red and green.
Reserved and should be set to zero.
This register determines the output of DAC 1. The full-scale output is determined by bit 5 of the DAC
Config, OSD Contrast & DC Offset Register.
GG6
BG6
RG6
CG6
GC6
BC6
6
6
6
6
6
6
GG5
BG5
RG5
CG5
GC5
BC5
5
5
5
5
5
5
(Continued)
GG4
BG4
RG4
CG4
GC4
BC4
4
4
4
4
4
4
36
GG3
BG3
RG3
CG3
GC3
BC3
3
3
3
3
3
3
GG2
BG2
RG2
CG2
GC2
BC2
2
2
2
2
2
2
GG1
BG1
RG1
CG1
GC1
BC1
1
1
1
1
1
1
GG0
RG0
CG0
GC0
BG0
BC0
0
0
0
0
0
0