DS90C387AVJD National Semiconductor, DS90C387AVJD Datasheet

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DS90C387AVJD

Manufacturer Part Number
DS90C387AVJD
Description
Manufacturer
National Semiconductor
Datasheet

Specifications of DS90C387AVJD

Number Of Elements
8
Input Type
CMOS/TTL
Operating Supply Voltage (typ)
3.3V
Differential Input High Threshold Voltage
100mV
Diff. Input Low Threshold Volt
-100mV
Output Type
Flat Panel Display
Differential Output Voltage
450mV
Operating Temp Range
-10C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
TQFP
Number Of Receivers
48
Number Of Drivers
8
Lead Free Status / RoHS Status
Not Compliant

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© 2006 National Semiconductor Corporation
DS90C387A/DS90CF388A
Dual Pixel LVDS Display Interface / FPD-Link
General Description
The DS90C387A/DS90CF388A transmitter/receiver pair is
designed to support dual pixel data transmission between
Host and Flat Panel Display up to QXGA resolutions. The
transmitter converts 48 bits (Dual Pixel 24-bit color) of
CMOS/TTL data and 3 control bits into 8 LVDS (Low Voltage
Differential Signalling) data streams. At a maximum dual
pixel rate of 112MHz, LVDS data line speed is 784Mbps,
providing a total throughput of 5.7Gbps (714 Megabytes per
second).
The LDI chipset is improved over prior generations of FPD-
Link devices and offers higher bandwidth support and longer
cable drive. To increase bandwidth, the maximum pixel clock
rate is increased to 112 MHz and 8 serialized LVDS outputs
are provided. Cable drive is enhanced with a user selectable
pre-emphasis feature that provides additional output current
during transitions to counteract cable loading effects.
The DS90C387A transmitter provides a second LVDS output
clock. Both LVDS clocks are identical. This feature supports
backward compatibility with the previous generation of FPD-
Link Receivers - the second clock allows the transmitter to
interface to panels using a ’dual pixel’ configuration of two
24-bit or 18-bit FPD-Link receivers.
This chipset is an ideal means to solve EMI and cable size
problems for high-resolution flat panel applications. It pro-
Generalized Transmitter Block Diagram
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
DS101320
vides a reliable interface based on LVDS technology that
delivers the bandwidth needed for high-resolution panels
while maximizing bit times, and keeping clock rates low to
reduce EMI and shielding requirements. For more details,
please refer to the “Applications Information” section of this
datasheet.
Features
n Supports SVGA through QXGA panel resolutions
n 32.5 to 112/170MHz clock support
n Drives long, low cost cables
n Up to 5.7 Gbps bandwidth
n Pre-emphasis reduces cable loading effects
n Dual pixel architecture supports interface to GUI and
n Transmitter rejects cycle-to-cycle jitter
n 5V tolerant on data and control input pins
n Programmable transmitter data and control strobe select
n Backward compatible with FPD-Link
n Compatible with ANSI/TIA/EIA-644-1995 LVDS Standard
timing controller; optional single pixel transmitter inputs
support single pixel GUI interface
(rising or falling edge strobe)
10132002
February 2006
www.national.com

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DS90C387AVJD Summary of contents

Page 1

... It pro- Generalized Transmitter Block Diagram TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2006 National Semiconductor Corporation vides a reliable interface based on LVDS technology that delivers the bandwidth needed for high-resolution panels while maximizing bit times, and keeping clock rates low to reduce EMI and shielding requirements. For more details, please refer to the “ ...

Page 2

Generalized Receiver Block Diagram Generalized Block Diagrams www.national.com 10132003 2 10132001 ...

Page 3

... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( CMOS/TTL Input Voltage CMOS/TTL Output Voltage −0. LVDS Receiver Input Voltage LVDS Driver Output Voltage LVDS Output Short Circuit ...

Page 4

Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter TRANSMITTER SUPPLY CURRENT ICCTW Transmitter Supply Current Worst Case Transmitter Supply Current 16 Grayscale ICCTZ Transmitter Supply Current Power Down RECEIVER SUPPLY CURRENT ICCRW Receiver Supply ...

Page 5

Recommended Transmitter Input Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol TCIT TxCLK IN Transition Time (Figure 5) TCIP TxCLK IN Period (Figure 6) TCIH TxCLK in High Time (Figure 6) TCIL TxCLK in Low Time ...

Page 6

Receiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol CLHT CMOS/TTL Low-to-High Transition Time (Figure 4), Rx data out CMOS/TTL Low-to-High Transition Time (Figure 4), Rx clock out CHLT CMOS/TTL High-to-Low Transition Time (Figure 4), ...

Page 7

AC Timing Diagrams FIGURE 2. “16 Grayscale” Test Pattern (Notes Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 8: The 16 grayscale test pattern tests ...

Page 8

AC Timing Diagrams FIGURE 3. DS90C387A (Transmitter) LVDS Output Load and Transition Times FIGURE 4. DS90CF388A (Receiver) CMOS/TTL Output Load and Transition Times FIGURE 5. DS90C387A (Transmitter) Input Clock Transition Time FIGURE 6. DS90C387A (Transmitter) Setup/Hold and High/Low Times (Falling ...

Page 9

AC Timing Diagrams (Continued) FIGURE 7. DS90CF388A (Receiver) Setup/Hold and High/Low Times FIGURE 8. DS90C387A (Transmitter) Phase Lock Loop Set Time FIGURE 9. DS90CF388A (Receiver) Phase Lock Loop Set Time 10132016 10132019 9 10132020 www.national.com ...

Page 10

AC Timing Diagrams C — Setup and Hold Time (Internal data sampling window) defined by RSPOS (receiver input strobe position) min and max TPPOS — Transmitter output pulse position (min and max) RSKM ≥ Cable Skew (type, length) + LVDS ...

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AC Timing Diagrams (Continued) FIGURE 14. Timing Diagram of the Input Cycle-to-Cycle Clock Jitter FIGURE 13. TJCC Test Setup - DS90C387A 11 10132027 10132028 www.national.com ...

Page 12

DS90C387A Pin Descriptions — FPD Link Transmitter Pin Name I/O Rn, Gn, Bn, I DE, HSYNC, VSYNC AnP O AnM O CLKIN I R_FB I R_FDE I CLK1P O CLK1M PLLSEL I PRE I DUAL I V ...

Page 13

DS90CF388A Pin Descriptions — FPD Link Receiver Pin Name I/O No. AnP I 8 AnM I 8 Rn, Gn, Bn DE, HSYNC, VSYNC RxCLK INP I 1 RxCLK INM I 1 RxCLK OUT O 1 R_FDE I 1 ...

Page 14

LVDS Interface / TFT Data (Color) Mapping Different color mapping options exist. See National Applica- tion Notes 1127 and 1163 for details. The LVDS Clock waveshape is shown in Figure 15. Note that the rising edge of the LVDS clock ...

Page 15

Applications Information HOW TO CONFIGURE THE DS90C387A AND DS90CF388A FOR MOST COMMON APPLICATION 1. To configure for single input pixel-to-dual pixel output application, the DS90C387 “DUAL” pin must be set to 1/2 Vcc=1.65V. This may be implemented using pull-up and ...

Page 16

Applications Information DS90C387/DS90CF388 The DS90C387A/CF388A chipset is electrically similar to the DS90C387/CF388. The DS90C387/CF388 is intended for improved support of longer cable drive. Cable drive is en- hanced with a user selectable pre-emphasis feature that provides additional output current during ...

Page 17

Pin Diagram Transmitter-DS90C387A 17 10132006 www.national.com ...

Page 18

Pin Diagram www.national.com Receiver-DS90CF388A 18 10132007 ...

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... Physical Dimensions inches (millimeters) unless otherwise noted Order Number DS90C387AVJD and DS90CF388AVJD National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. ...

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