MC34910G5AC Freescale, MC34910G5AC Datasheet - Page 83

• Manufacturer Part Number: MC34910G5AC
• Manufacturer: Freescale

Specifications of MC34910G5AC

• Turn Off Delay Time: 10us
• Number Of Drivers: 2
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant

CYSTx - Cyclic Sense Period Prescaler Select
cyclic sensing together with the bit CYSX8 in the
configuration register (CFR) (see
CFR).
when entering in Stop or Sleep mode. Otherwise a timed
wake-up is performed after the period shown in
Table 51.
Watchdog Status Register
is also returned when writing to the TIMCR.
WDTO - Watchdog Time Out
either a watchdog timeout or by an attempt to clear the
watchdog within the window closed.
WDTO bit.
83
33910
CYSX8
Notes
123.
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
This write-only bits selects the interval for the wake-up
This option is only active if the high side switch is enabled
This register returns the watchdog status information and
This read-only bit signals the last reset was caused by
Any access to this register or the TIMCR will clear the
X
0
0
0
0
0
0
0
1
1
1
1
1
1
1
bit CYSX8 is located in configuration register (CFR)
(123)
Table 52. Watchdog Status Register - $A/$B
Read
Cyclic Sense Interval
CYST2
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
WDTO
S3
CYST1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
WDERR
S2
CYST0
Configuration Register -
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
WDOFF
S1
No Cyclic Sense
WDWO
S0
1120 ms
Interval
Table
100 ms
120 ms
140 ms
160 ms
320 ms
480 ms
640 ms
800 ms
960 ms
20 ms
40 ms
60 ms
80 ms
51.
WDERR - Watchdog Error
watchdog resistor. In this condition the watchdog is using the
internal, lower precision timebase. The windowing function is
disabled.
WDOFF - Watchdog Off
to GND and therefore disabled. In this case watchdog
timeouts are disabled and the device automatically enters
Normal mode out of Reset. This might be necessary for
software debugging and for programming the Flash memory.
WDWO - Watchdog Window Open
open for clears. The purpose of this bit is for testing. Should
be ignored in case WDERR is High.
Analog Multiplexer Control Register - MUXCR
the divider ration for the L1 input divider.
L1DS - L1 Analog Input Divider Select
analog input. Voltage is internally clamped to VDD.
1 = Last reset caused by watchdog timeout
0 = None
This read-only bit signals the detection of a missing
1 = WDCONF pin resistor missing
0 = WDCONF pin resistor not floating
This read-only bit signals that the watchdog pin connected
1 = Watchdog is disabled
0 = Watchdog is enabled
This read-only bit signals when the watchdog window is
1 = Watchdog window open
0 = Watchdog window closed
This register controls the analog multiplexer and selects
This write-only bit selects the resistor divider for the L1
0 = L1 Analog divider: 1
1 = L1 Analog divider: 3.6 (typ.)
Table 53. Analog Multiplexer Control Register -$C
Reset Condition
Reset Value
Write
L1DS
POR
C3
Analog Integrated Circuit Device Data
1
POR, Reset mode or ext_reset
MX2
C2
0
Freescale Semiconductor
MX1
C1
0
MX0
C0
0