MC33912G5AC Freescale, MC33912G5AC Datasheet - Page 46

• Manufacturer Part Number: MC33912G5AC
• Manufacturer: Freescale

Specifications of MC33912G5AC

• Turn Off Delay Time: 10us
• Number Of Drivers: 4
• Operating Temperature (min): -40C
• Operating Temperature (max): 125C
• Operating Temperature Classification: Automotive
• Lead Free Status / RoHS Status: Compliant

Interrupt Mask Register - IMR
sources. No interrupt will be generated to the MCU and no
flag will be set in the ISR register. The 5.0 V Regulator over-
temperature prewarning interrupt and under-voltage (VSUV)
interrupts can not be masked and will always cause an
interrupt.
HSM - High Side Interrupt Mask
the high side block.
LSM - Low Side Interrupt Mask
the low side block.
Table 32. Interrupt Sources
46
33912
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
ISR3 ISR2 ISR1 ISR0
0
0
0
0
0
0
0
This register allows masking of some of the interrupt
Writing to the IMR will return the ISR.
This write-only bit enables/disables interrupts generated in
1 = HS Interrupts Enabled
0 = HS Interrupts Disabled
This write-only bit enables/disables interrupts generated in
1 = LS Interrupts Enabled
0 = LS Interrupts Disabled
Table 30. Interrupt Mask Register - $E
Condition
0
0
0
0
1
1
1
Reset
Reset
Value
Write
0
0
1
1
0
0
1
HSM
C3
1
0
1
0
1
0
1
0
(Low Voltage and VDD over-temperature)
LSM
C2
Lx Wake-up from Stop and Sleep mode
1
POR
Voltage Monitor Interrupt
LINM
C1
1
Forced Wake-up
none maskable
LIN Wake-up
no interrupt
VMM
-
-
C0
1
Interrupt Source
LINM - LIN Interrupts Mask
the LIN block.
VMM - Voltage Monitor Interrupt Mask
the Voltage Monitor block. The only maskable interrupt in the
Voltage Monitor Block is the V
Interrupt Source Register - ISR
the last interrupt or wake-up respectively. A read of the
register acknowledges the interrupt and leads IRQ pin to
high, in case there are no other pending interrupts. If there
are pending interrupts, IRQ will be driven high for 10 µs and
then be driven low again.
Mask Register (IMR).
ISRx - Interrupt Source Register
Table
sources are handled sequentially multiplex.
This write-only bit enables/disables interrupts generated in
1 = LIN Interrupts Enabled
0 = LIN Interrupts Disabled
This write-only bit enables/disables interrupts generated in
1 = Interrupts Enabled
0 = Interrupts Disabled
This register allows the MCU to determine the source of
This register is also returned when writing to the Interrupt
These read-only bits indicate the interrupt source following
In case more than one interrupt is pending, the interrupt
LIN Interrupt (RXSHORT, TXDOM, LIN OT)
32. If no interrupt is pending then all bits are 0.
Table 31. Interrupt Source Register - $E/$F
HS Interrupt (Over-temperature)
LS Interrupt (Over-temperature)
Read
Voltage Monitor Interrupt
(High Voltage)
no interrupt
maskable
ISR3
S3
Analog Integrated Circuit Device Data
-
-
ISR2
S2
SUP
over-voltage interrupt.
Freescale Semiconductor
ISR1
S1
ISR0
S0
Priority
highest
lowest
none