NE5537N NXP Semiconductors, NE5537N Datasheet - Page 8

• Manufacturer Part Number: NE5537N
• Manufacturer: NXP Semiconductors

Specifications of NE5537N

• Number Of Sample And Hold Elements: 1
• Power Supply Requirement: Dual
• Single Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Package Type: PDIP
• Lead Free Status / RoHS Status: Compliant

instance, may “sag back” up to 0.2% after a quick change in voltage.
unusable with >1% hysteresis. The advantage of polypropylene over
significant concern to designers employing sample-and-hold circuits.
will add an RC time constant, over and above the slew rate limitation
Philips Semiconductors
APPLICATION HINTS
Hold Capacitor
A significant source of error in an accurate sample-and-hold circuit
is dielectric absorption in the hold capacitor. A mylar cap, for
A long “soak” time is required before the circuit can be put back in
the hold mode with this type of capacitor. Dielectrics with very low
hysteresis are polystyrene, polypropylene, and teflon. Other types
such as mica and polycarbonate are not nearly as good. Ceramic is
polystyrene is that it extends the maximum ambient temperature
from 85 C to 100 C. The hysteresis relaxation time constant in
polystyrene, for instance, is 10–50 ms. If A-to-D conversion can be
made within 1 ms, hysteresis error will be reduced by a factor of ten.
DC ZEROING
DC zeroing is accomplished by connecting the offset adjust pin to
the wiper of a 1 k potentiometer which has one end tied to V+ and
the other end tied through a resistor to ground. The resistor should
be selected to give 0.6mA through the 1 k potentiometer.
Sampling Dynamic Signals
Sampling errors due to moving (changing) input signals are of
There exist finite phase delays through the sample-and-hold circuit
causing an input-output phase of differential for moving signals. In
addition, the series protection resistor (300
of the input buffer/current drive amplifier. This means that at the
moment the “HOLD” command arrives, the hold capacitor voltage
may be somewhat different from the actual analog input. The effect
of these delays is opposite to the effect created by delays in the
logic which switches the circuit from sample to hold. For example,
consider an analog input of 20 V
0.6 V/ s. With no analog phase delay and 100 ns logic delay, one
could expect up to (0.1 s) (0.6 V/ s) = 60 mV error if the “HOLD”
signal arrived near maximum dV/dt of the input. A positive-going
input would give a 60 mV error. Now assume a 1 MHz (3 dB)
2001 Aug 03
Sample-and-hold amplifier
P-P
at 10 kHz. Maximum dV/dt is
to Pin 6 of the NE5537)
8
total of –36 mV. To add to the confusion, analog delay is proportional
may experience a sudden change nearly coincident with the “HOLD”
bandwidth for the overall analog loop. This generates a phase delay
of 160 ns. If the hold capacitor sees this exact delay, then error due
to analog delay will be (0.16 s) (0.6 V/ s) = –96 mV (analog) for a
to hold capacitor value, while digital delay remains constant. A
family of curves (dynamic sampling error) is included to help
estimate errors.
A curve labeled “Aperture Time” has been included for sampling
conditions where the input is steady during the sampling period, but
command. This curve is based on a 1 mV error fed into the output.
A second curve, “Hold Settling Time,” indicates the time required for
the output to settle to 1 mV after the “HOLD” command.
Digital Feedthrough
Fast rise time logic signals can cause hold errors by feeding
externally into the analog input at the same time the amplifier is put
into the hold mode. To minimize this problem, board layout should
keep logic lines as far as possible from the analog input. Grounded
guarding traces may also be used around the input line, especially if
it is driven from a high impedance source. Reducing high amplitude
logic signals to 2.5 V will also help.
Logic signals also couple to the hold capacitor. This hold capacitor
should be guarded by a PC card trace connected to the
sample-and-hold output. This will also minimize board leakage.
SPECIAL NOTES
1. Not all definitions herein defined are measured parametrically for
2. Reference should be made to Design Engineering , Volumes 23
3. Reference also made to National Semiconductor Corporation’s
the NE5537, but are legitimate terms used in sample-and-hold
systems.
(Nov. 8, 1978), 25 (Dec. 6, 1978) and 26 (Dec. 20, 1978) for
articles written by Eugene Zuch of Datel Systems, Inc., for a
further discussion of sample-and-hold circuits.
Special Functions Data Book (1976).
NE5537
Product data