SE5537FE NXP Semiconductors, SE5537FE Datasheet - Page 7

• Manufacturer Part Number: SE5537FE
• Manufacturer: NXP Semiconductors

Specifications of SE5537FE

• Number Of Sample And Hold Elements: 1
• Power Supply Requirement: Dual
• Single Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Mounting: Through Hole
• Package Type: PDIP
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors Linear Products
The switch mechanism is on (sampling an information stream) when
the logic level is high (Pin 8 is 1.4V higher than Pin 7) and presents
a load of 5 A to the input logic signal. The analog sampled signal is
amplified, stored (in the external holding capacitor), and buffered. At
the end of the sampling period, the internal switch mechanism turns
off (switch opens) and the “stored analog memory” information on
the external capacitor (Pin 6) is loaded down by an operational
amplifier connected in the unity gain non-inverting configuration.
This input impedance of this amplifier is effectively:
Therefore, the higher the open-loop gain of the second operational
amplifier, the larger the effective loading on the capacitor. The larger
the load, the lower the “leakage” current and the better the droop
characteristics.
In actuality, the amplifiers are designed with special leakage current
cancellation circuits along with FET input devices. The leakage
current cancellation circuits give better high temperature operation.
(Remember that the FET amplifiers double in required bias current
for every 10 degree increase in junction temperature.)
Sampling time for the NE5537 is less than 10 s (measured to 0.1%
of input signal). Leakage current is 6pA at a rate output load of 2k .
BASIC APPLICATIONS
Multiplying DAC
As depicted in the block diagram of Figure 2, the sample-and-hold
circuit is used to supply a “variable” reference to the digital-to-analog
converter. As the input reference varies, the output will change in
accordance with Equation 1, shown in Figure 2.
Varying the input signal reference level can aid the system in
performing both compression and expansion operations. The
multiplying DACs used are the Philips Semiconductors NE/SE5008;
however, if the rate of change of the reference variation is kept slow
enough, a microprocessor-compatible DAC can be incorporated,
such as the NE5018 or the NE5020.
August 31, 1994
where R
Sample-and-hold amplifier
R
R
A
A
IN
OL
SAMPLE
HOLD
= R
= Effective input impedance
= Open-loop input impedance
= Open-loop gain
= AC loop gain
Figure 1. Typical Connection
ANALOG INPUT
IN
5V
0V
(A
OL
) / (1 + 1/A)
LOGIC
INPUT
3
8
V+
1
7
V–
4
6
5
C
h
OUTPUT
890
DATA ACQUISITION SYSTEMS
As mentioned earlier, the designer may wish to operate on several
different segments of an “analog” signal; however, he is limited by
the fact that only one analog-to-digital converter channel is available
to him. Figure 3 shows the means by which a multiplexing system
may be accomplished.
APPLICATION HINTS
Hold Capacitor
A significant source of error in an accurate sample-and-hold circuit
is dielectric absorption in the hold capacitor. A mylar cap, for
instance, may “sag back” up to 0.2% after a quick change in voltage.
A long “soak” time is required before the circuit can be put back in
the hold mode with this type of capacitor. Dielectrics with very low
hysteresis are polystyrene, polypropylene, and teflon. Other types
such as mica and polycarbonate are not nearly as good. Ceramic is
unusable with >1% hysteresis. The advantage of polypropylene over
polystyrene is that it extends the maximum ambient temperature
from 85 C to 100 C. The hysteresis relaxation time constant in
polystyrene, for instance, is 10-50ms. If A-to-D conversion can be
made within 1ms, hysteresis error will be reduced by a factor of ten.
DC ZEROING
DC zeroing is accomplished by connecting the offset adjust pin to
the wiper of a 1k potentiometer which has one end tied to V+ and
the other end tied through a resistor to ground. The resistor should
be selected to give 0.6mA through the 1k potentiometer.
Sampling Dynamic Signals
Sampling errors due to moving (changing) input signals are of
significant concern to designers employing sample-and-hold circuits.
There exist finite phase delays through the sample-and-hold circuit
causing an input-output phase of differential for moving signals. In
addition, the series protection resistor (300 to Pin 6 of the NE5537)
will add an RC time constant, over and above the slew rate limitation
of the input buffer/current drive amplifier. This means that at the
moment the “HOLD” command arrives, the hold capacitor voltage
may be somewhat different from the actual analog input. The effect
of these delays is opposite to the effect created by delays in the
logic which switches the circuit from sample to hold. For example,
consider an analog input of 20 V
0.6V/ s. With no analog phase delay and 100ns logic delay, one
could expect up to (0.1 s) (0.6V/ s) =60mV error if the “HOLD”
signal arrived near maximum dV/dt of the input. A positive-going
input would give a 60mV error. Now assume a 1MHz (3dB)
bandwidth for the overall analog loop. This generates a phase delay
of 160ns. If the hold capacitor sees this exact delay, then error due
to analog delay will be (0.16 s) (0.6V/ s)=-96mV (analog) for a total
of -36mV. To add to the confusion, analog delay is proportional to
hold capacitor value, while digital delay remains constant. A family
of curves (dynamic sampling error) is included to help estimate
errors.
P-P
at 10kHz. Maximum dV/dt is
NE/SE5537
Product specification