LF198H/883 National Semiconductor, LF198H/883 Datasheet - Page 11

• Manufacturer Part Number: LF198H/883
• Manufacturer: National Semiconductor

Specifications of LF198H/883

• Number Of Sample And Hold Elements: 1
• Power Supply Requirement: Dual
• Single Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Mounting: Through Hole
• Lead Free Status / RoHS Status: Not Compliant

Application Hints
HOLD CAPACITOR
Hold step, acquisition time, and droop rate are the major
trade-offs in the selection of a hold capacitor value. Size and
cost may also become important for larger values. Use of the
curves included with this data sheet should be helpful in
selecting a reasonable value of capacitance. Keep in mind
that for fast repetition rates or tracking fast signals, the
capacitor drive currents may cause a significant temperature
rise in the LF198.
A significant source of error in an accurate sample and hold
circuit is dielectric absorption in the hold capacitor. A mylar
cap, for instance, may “sag back” up to 0.2% after a quick
change in voltage. A long sample time is required before the
circuit can be put back into the hold mode with this type of
capacitor. Dielectrics with very low hysteresis are polysty-
rene, polypropylene, and Teflon. Other types such as mica
and polycarbonate are not nearly as good. The advantage of
polypropylene over polystyrene is that it extends the maxi-
mum ambient temperature from 85˚C to 100˚C. Most ce-
ramic capacitors are unusable with
ramic “NPO” or “COG” capacitors are now available for
125˚C operation and also have low dielectric absorption. For
more exact data, see the curve Dielectric Absorption Error.
The hysteresis numbers on the curve are final values, taken
after full relaxation. The hysteresis error can be significantly
reduced if the output of the LF198 is digitized quickly after
the hold mode is initiated. The hysteresis relaxation time
constant in polypropylene, for instance, is 10 — 50 ms. If
A-to-D conversion can be made within 1 ms, hysteresis error
will be reduced by a factor of ten.
DC AND AC ZEROING
DC zeroing is accomplished by connecting the offset adjust
pin to the wiper of a 1 kΩ potentiometer which has one end
tied to V
The resistor should be selected to give ≈0.6 mA through the
1k potentiometer.
AC zeroing (hold step zeroing) can be obtained by adding an
inverter with the adjustment pot tied input to output. A 10 pF
capacitor from the wiper to the hold capacitor will give
hold step adjustment with a 0.01 µF hold capacitor and 5V
logic supply. For larger logic swings, a smaller capacitor
(
LOGIC RISE TIME
For proper operation, logic signals into the LF198 must have
a minimum dV/dt of 1.0 V/µs. Slower signals will cause
excessive hold step. If a R/C network is used in front of the
logic input for signal delay, calculate the slope of the wave-
form at the threshold point to ensure that it is at least
1.0 V/µs.
SAMPLING DYNAMIC SIGNALS
Sample error to moving input signals probably causes more
confusion among sample-and-hold users than any other pa-
rameter. The primary reason for this is that many users make
the assumption that the sample and hold amplifier is truly
locked on to the input signal while in the sample mode. In
actuality, there are finite phase delays through the circuit
creating an input-output differential for fast moving signals.
<
10 pF) may be used.
+
and the other end tied through a resistor to ground.
>
1% hysteresis. Ce-
±
4 mV
11
In addition, although the output may have settled, the hold
capacitor has an additional lag due to the 300Ω series
resistor on the chip. This means that at the moment the
“hold” command arrives, the hold capacitor voltage may be
somewhat different than the actual analog input. The effect
of these delays is opposite to the effect created by delays in
the logic which switches the circuit from sample to hold. For
example, consider an analog input of 20 Vp-p at 10 kHz.
Maximum dV/dt is 0.6 V/µs. With no analog phase delay and
100 ns logic delay, one could expect up to (0.1 µs) (0.6V/µs)
= 60 mVerror if the “hold” signal arrived near maximum dV/dt
of the input. A positive-going input would give a +60 mV
error. Now assume a 1 MHz (3 dB) bandwidth for the overall
analog loop. This generates a phase delay of 160 ns. If the
hold capacitor sees this exact delay, then error due to analog
delay will be (0.16 µs) (0.6 V/µs) = −96 mV. Total output error
is +60 mV (digital) −96 mV (analog) for a total of −36 mV. To
add to the confusion, analog delay is proportioned to hold
capacitor value while digital delay remains constant. A family
of curves (dynamic sampling error) is included to help esti-
mate errors.
A curve labeled Aperture Time has been included for sam-
pling conditions where the input is steady during the sam-
pling period, but may experience a sudden change nearly
coincident with the “hold” command. This curve is based on
a 1 mV error fed into the output.
A second curve, Hold Settling Time indicates the time re-
quired for the output to settle to 1 mV after the “hold”
command.
DIGITAL FEEDTHROUGH
Fast rise time logic signals can cause hold errors by feeding
externally into the analog input at the same time the amplifier
is put into the hold mode. To minimize this problem, board
layout should keep logic lines as far as possible from the
analog input and the C
also be used around the input line, especially if it is driven
from a high impedance source. Reducing high amplitude
logic signals to 2.5V will also help.
Use 10-pin layout. Guard around C
Guarding Technique
h
pin. Grounded guarding traces may
h
is tied to output.
20122205
www.national.com