UDA1344TS/N2,112 NXP Semiconductors, UDA1344TS/N2,112 Datasheet - Page 10

• Manufacturer Part Number: UDA1344TS/N2,112
• Manufacturer: NXP Semiconductors

Specifications of UDA1344TS/N2,112

• Single Supply Voltage (typ): 3V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 3.6V
• Package Type: SSOP
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
L3 mode
The UDA1344TS is set to the L3 mode by setting both
pins MC1 and MC2 to LOW level.
The static pins in this mode are used for:
• ADC output overload detection
• L3 interface signal input
• ADC input voltage selection.
The controllable features via the L3 interface and the
definition of the control registers are given in
Section “L3 interface”.
P
The pinning definition in the L3 mode is given in Table 11.
Table 11 Pinning definition in L3 mode
2001 Jun 29
INNING DEFINITION
Low-voltage low-power stereo audio
CODEC with DSP features
MP1
MP2
MP3
MP4
MP5
PIN
ADC output overload detection
L3MODE input
L3CLOCK input
L3DATA input
ADC input voltage selection:
1 V (RMS) or 2 V (RMS)
FUNCTION
10
ADC
In practice the output is used to indicate whenever the
output data, in either the left or right channel, is greater
than −1 dB (actual figure is −1.16 dB) of the maximum
possible digital swing. When this condition is detected
pin MP1 is forced to HIGH level for at least 512f
(11.6 ms at f
infringement.
ADC
In the L3 mode pin MP5 is used to select 0 or 6 dB gain.
Table 12 Levels for pin MP5
OUTPUT OVERLOAD DETECTION
INPUT VOLTAGE SELECTION
PIN MP4
HIGH
LOW
s
= 44.1 kHz). This time-out is reset for each
0 dB gain
6 dB gain
SELECTION
UDA1344TS
Product specification
s
cycles