UDA1342TS/N1,112 NXP Semiconductors, UDA1342TS/N1,112 Datasheet - Page 34

UDA1342TS/N1,112

Manufacturer Part Number
UDA1342TS/N1,112
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of UDA1342TS/N1,112

Single Supply Voltage (typ)
3V
Single Supply Voltage (min)
2.7V
Single Supply Voltage (max)
3.6V
Package Type
SSOP
Lead Free Status / RoHS Status
Compliant
NXP Semiconductors
16 TIMING
V
specified.
2000 Jul 31
System clock timing; note 1 (see Fig.11)
T
t
t
Serial interface input/output data timing (see Fig.12)
f
T
t
t
t
t
t
t
t
t
t
t
t
L3-bus interface timing (see Figs 13 and 14)
t
t
T
t
t
t
t
DDD
CWL
CWH
BCK
BCKH
BCKL
r
f
su(WS)
h(WS)
su(DATAI)
h(DATAI)
h(DATAO)
d(DATAO-BCK)
d(DATAO-WS)
r
f
CLK(L3)H
CLK(L3)L
su(L3)A
h(L3)A
sys
cy(BCK)
cy(CLK)L3
Audio CODEC
SYMBOL
SYMBOL
= V
DDA(ADC)
system clock cycle time
system clock LOW time
system clock HIGH time
bit clock frequency
bit clock cycle time
bit clock HIGH time
bit clock LOW time
rise time
fall time
word select set-up time
word select hold time
data input set-up time
data input hold time
data output hold time
data output to bit clock delay
data output to word select delay
rise time
fall time
L3CLOCK cycle time
L3CLOCK HIGH time
L3CLOCK LOW time
L3MODE set-up time in address
mode
L3MODE hold time in address
mode
= V
DDA(DAC)
PARAMETER
PARAMETER
= 2.7 to 3.6 V; T
amb
= −20 to +85 °C; all voltages referenced to ground; unless otherwise
f
f
f
f
f
f
f
f
T
frequency cycle time
note 2
note 2
note 3
sys
sys
sys
sys
sys
sys
sys
sys
cy(s)
CONDITIONS
CONDITIONS
= 256f
= 384f
= 512f
= 768f
< 19.2 MHz
≥ 19.2 MHz
< 19.2 MHz
≥ 19.2 MHz
= sample
34
s
s
s
s
35
23
17
17
0.3T
0.4T
0.3T
0.4T
30
30
10
10
10
10
0
500
250
250
190
190
MIN.
MIN.
sys
sys
sys
sys
81
54
41
27
TYP.
TYP.
UDA1342TS
250
170
130
90
0.7T
0.6T
0.7T
0.6T
128f
1
20
20
30
30
10
10
Product specification
128
MAX.
MAX.
T
s
sys
sys
sys
sys
cy(s)
ns
ns
ns
ns
ns
ns
ns
ns
Hz
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns/V
ns/V
ns
ns
ns
ns
ns
UNIT
UNIT

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