SAA7154E/V2/G,557 NXP Semiconductors, SAA7154E/V2/G,557 Datasheet - Page 87

• Manufacturer Part Number: SAA7154E/V2/G,557
• Manufacturer: NXP Semiconductors

Specifications of SAA7154E/V2/G,557

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
20. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. Clock and real-time synchronization signals . .35
Table 11. Signals dedicated to the expansion port . . . . .37
Table 12. Availability of control signals for 50 Hz/625
Table 13. Signals dedicated to the image port . . . . . . . .42
Table 14. Digital OSD . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Table 15. I
Table 16. Register 00h used by chip version part . . . . . .44
Table 17. Registers 01h to 1Fh used by the video
Table 18. Register 20h to 2Fh used for component
Table 19. Registers 30h to 3Fh used by audio clock
Table 20. Registers 40h to 7Fh used by general
Table 21. Registers 80h to 8Fh used by task
Table 22. Registers 90h to BFh used for task A
Table 23. Registers C0h to EFh used for task B
Table 24. I
Table 25. Register 00h to 1Fh used by
Table 26. Registers 20h to 3Fh used by Analog Input
Table 27. Registers 40h to 4Fh used by Analog Input
Table 28. Registers 50h to 59h used by color
Table 29. Registers 60h to 78h used by OSD . . . . . . . .57
Table 30. Registers 80h to 8Bh used by edge-guided
Table 31. Registers 8Ch to BFh used by scaler post
SAA7154E_SAA7154H_2
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .4
Pin allocation table LBGA156 package
Pin allocation table QFP160 package
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .9
60 Hz/525 lines VBI data types supported by
the data slicer block . . . . . . . . . . . . . . . . . . . . .28
50 Hz/625 Lines VBI data types supported by
the data slicer block . . . . . . . . . . . . . . . . . . . . .29
List of status signals for which an interrupt
can be initiated . . . . . . . . . . . . . . . . . . . . . . . . .31
Analog pin description . . . . . . . . . . . . . . . . . . .34
Audio clock pin description . . . . . . . . . . . . . . .35
and 60 Hz/525 line systems . . . . . . . . . . . . . . .37
decoder part . . . . . . . . . . . . . . . . . . . . . . . . . .44
processing and interrupt masking . . . . . . . . . .45
generator
purpose VBI data slicer
independent global settings 1 . . . . . . . . . . . . .48
definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
HDTV-synchronization . . . . . . . . . . . . . . . . . .54
Control (AIC) expert mode and extended
analog input/output functions . . . . . . . . . . . . .54
Control (AIC) expert mode status (read only) .56
improvement (gravity functions) . . . . . . . . . . .56
interpolation . . . . . . . . . . . . . . . . . . . . . . . . . .58
2
2
C-bus basic functions overview . . . . . . . . . . .43
C-bus extended functions overview . . . . . . . .53
. . . . . . . . . . . . . . . . . . . . . . . . . . . .46
. . . . . . . . . . . . . . . . .46
[1]
Rev. 02 — 6 December 2007
[1]
. . . . . . .8
. . . . .6
Table 32. Registers C0h to CFh used by histogram
Table 33. Registers D0h to DFh used by histogram
Table 34. Registers E0h to FFh used by second PLL/CG
Table 35. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 36. Thermal characteristics . . . . . . . . . . . . . . . . . . 64
Table 37. Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 38. Analog part . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 39. Digital inputs and outputs . . . . . . . . . . . . . . . . 66
Table 40. Clocks and oscillators . . . . . . . . . . . . . . . . . . . 67
Table 41. X-port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 42. I-port, IX-port and H-port . . . . . . . . . . . . . . . . . 69
Table 43. Voltage ranges . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 44. Relationship between logic levels and ADC
Table 45. BST instructions supported by the SAA7154E;
Table 46. SnPb eutectic process (from J-STD-020C) . . . 80
Table 47. Lead-free process (from J-STD-020C) . . . . . . 80
Table 48. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 49. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 84
SAA7154E; SAA7154H
Multistandard video decoder with comb filter
processing look-up tables
collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
(PLL2/CG2) and raster generator . . . . . . . . . . 61
slices for different applications . . . . . . . . . . . . 74
SAA7154H . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
. . . . . . . . . . . . . . . 58
© NXP B.V. 2007. All rights reserved.
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