ADV7314KST Analog Devices Inc, ADV7314KST Datasheet - Page 6

• Manufacturer Part Number: ADV7314KST
• Manufacturer: Analog Devices Inc

Specifications of ADV7314KST

• Number Of Dac's: 6
• Adc/dac Resolution: 14b
• Screening Level: Commercial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

ADV7314
TIMING SPECIFICATIONS
Parameter
MPU PORT
ANALOG OUTPUTS
CLOCK CONTROL AND PIXEL PORT
PIPELINE DELAY
NOTES
1
2
3
4
Specifications subject to change without notice.
Guaranteed by characterization.
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.
Data: C [9:0]; Y [9:0], S[9:0]
SD, PS = 27 MHz, HD = 74.25 MHz.
Control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, S_VSYNC, S_BLANK.
SCLOCK Frequency
SCLOCK High Pulsewidth, t
SCLOCK Low Pulsewidth, t
Hold Time (Start Condition), t
Setup Time (Start Condition), t
Data Setup Time, t
SDATA, SCLOCK Rise Time, t
SDATA, SCLOCK Fall Time, t
Setup Time (Stop Condition), t
RESET Low Time
Analog Output Delay
Output Skew
f
f
Clock High Time t
Clock Low Time t
Data Setup Time t
Data Hold Time t
SD Output Access Time t
SD Output Hold Time t
HD Output Access Time t
HD Output Hold Time t
CLK
CLK
1
4
12
10
11
9
5
1
1
2
14
14
13
13
2
1
3
8
4
7
6
(V
3040
AA
3
= 2.375 V–2.625 V, V
, R
Min
0
0.6
1.3
0.6
0.6
100
0.6
100
40
40
2.0
2.0
5.0
5.0
LOAD
= 150
Typ
7
1
81
63
76
35
41
36
. All specifications T
DD
–6–
= 2.375 V–2.625 V; V
Max
400
300
300
27
15
14
Unit
kHz
ms
ms
ms
ms
ns
ns
ns
ms
ns
ns
ns
MHz
MHz
% of one clk cycle
% of one clk cycle
ns
ns
ns
ns
ns
ns
clk cycles
clk cycles
clk cycles
clk cycles
clk cycles
MIN
to T
DD_IO
MAX
= 2.375 V–3.6 V, V
(0 C to 70 C), unless otherwise noted.)
Conditions
The first clock is generated after
this period
Relevant for repeated start
condition
Progressive Scan Mode
HDTV Mode/ASYNC Mode
SD [2 , 16 ]
SD Component Mode [16 ]
PS [1 ]
PS [8 ]
HD [2 , 1 ]
REF
= 1.235 V, R
SET
=
REV. 0