ADV7314KST Analog Devices Inc, ADV7314KST Datasheet - Page 38

• Manufacturer Part Number: ADV7314KST
• Manufacturer: Analog Devices Inc

Specifications of ADV7314KST

• Number Of Dac's: 6
• Adc/dac Resolution: 14b
• Screening Level: Commercial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

ADV7314
Reset Sequence
A reset is activated with a high-to-low transition on the RESET pin
[Pin 33] according to the timing specifications. The ADV7314
will revert to the default output configuration. Figure 32 illus-
trates the RESET sequence timing.
SD VCR FF/RW Sync
[Subaddress 42h, Bit 5]
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW Sync control bit can be used for non-
standard input video, i.e., in fast forward or rewind modes.
In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct
number of lines/field are reached. In rewind mode, this sync
DIGITAL TIMING
PIXEL DATA
2
3
NOTES
1
RTC
SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED; NTSC: 0 = NO CHANGE
SEQUENCE BIT
RESET ADV7314 DDS
PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS
OF THE ADV7314.
F
SC
RESET
A, B, C
VALID
PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7314 F
DACs
COMPOSITE
OR CABLE
XXXXXX
XXXXXX
e.g., VCR
H/L TRANSITION
COUNT START
VIDEO
TIME SLOT 01
128
LOW
ADV7183A
DECODER
VIDEO
13
LCC1
SUBCARRIER
PHASE
14 BITS
Figure 31. RTC Timing and Connections
P19–P10
Figure 32. RESET Timing Sequence
RESERVED
GLL
14
0
4 BITS
DIGITAL TIMING SIGNALS SUPPRESSED
21
19
–38–
CLKIN_A
RTC_SCR_TR
Y9-Y0/S9–S0*
OFF
SC
SAMPLE
signal usually occurs after the total number of lines/field are
reached. Conventionally this means that the output video will
have corrupted field signals, one generated by the incoming
video and one when the internal lines/field counters reach the
end of a field.
When the VCR FF/RW sync control is enabled [Subaddress 42h,
Bit 5] the lines/field counters are updated according to the
incoming VSYNC signal and the analog output matches the
incoming VSYNC signal.
This control is available in all slave timing modes except Slave
Mode 0.
F
ADV7314
VALID
SC
DDS REGISTER IS F
PLL INCREMENT
SAMPLE
INVALID
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
1
SC
PLL INCREMENTS BITS 21:0
LOCKED
CLOCK
8/LINE
*SELECTED BY REGISTER
ADDRESS 01h BIT 7
SEQUENCE
BIT
0
2
RESERVED
6768
5 BITS
RESET
RESERVED
BIT
3
TIMING ACTIVE
VALID VIDEO
REV. 0