ADV7181CBCPZ Analog Devices Inc, ADV7181CBCPZ Datasheet - Page 16

• Manufacturer Part Number: ADV7181CBCPZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7181CBCPZ

• Adc/dac Resolution: 10b
• Screening Level: Industrial
• Package Type: LFCSP EP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

ADC0_SW_SEL[3:0]
ADV7181C
On the ADV7181C, it is recommended to use the ADC mapping shown in Table 8.
Table 8. Recommended ADC Mapping
Mode
CVBS
YC/YC auto
Component YUV
Component YUV
SCART RGB
Graphics
RGB Mode
1
Table 9. Manual MUX Settings for All ADCs
0001
0010
0100
0101
0110
1100
The analog input muxes of the ADV7181C must be controlled
directly. This is referred to as manual input muxing. The manual
muxing is activated by setting the ADC_SWITCH_MAN bit
(see Table 9). It affects only the analog switches in front of the
ADCs. INSEL, SDM_SEL, PRIM_MODE, and VID_STD still
have to be set so that the follow-on blocks process the video
data in the correct format.
Not every input pin can be routed to any ADC. There are
restrictions in the channel routing imposed by the analog signal
routing inside the IC. See Table 9 for an overview of the routing
capabilities inside the chip. The four mux sections can be
controlled by the reserved control signal buses ADC0_SW[3:0]/
ADC1_SW[3:0]/ADC2_SW[3:0]/ADC3_SW[3:0].
Configuration to format follow-on blocks in correct format.
Required ADC Mapping
Y = ADC0
Y = ADC0
CBVS = ADC0
G = ADC0
B = ADC2
ADC0
Y = ADC0
C = ADC1
U = ADC2
V = ADC1
U = ADC2
V = ADC1
G = ADC1
B = ADC3
R = ADC2
R = ADC1
ADC0
Connection ADC1_SW_SEL[3:0]
A
A
A
A
A
A
IN
IN
IN
IN
IN
IN
1
2
4
5
6
3
0001
0010
0100
0101
0110
1100
AIN Channel
CVBS = A
Y = A
C = A
Y = A
U = A
V = A
Y = A
U = A
V = A
CVBS = A
G = A
B = A
R = A
G = A
B = A
R = A
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
2
6
5
6
5
4
5
4
5
3
4
4
6
6
ADC1
Connection ADC2_SW_SEL[3:0]
ADC_SWITCH_MAN to 1
N/A
N/A
A
A
A
A
IN
IN
IN
IN
IN
IN
4
5
6
3
1
2
Rev. C | Page 16 of 20
Core
SD
SD
SD
CP
SD
CP
0001
0010
0100
0101
0110
1100
Table 9 explains the ADC mapping configuration for the following:
•
•
•
•
•
Configuration
INSEL[3:0] = 0000
SDM_SEL[1:0] = 00
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 0010
INSEL[3:0] = 0000
SDM_SEL[1:0] = 11
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 0010
INSEL[3:0] = 1001
SDM_SEL[1:0] = 00
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 0010
INSEL[3:0] = 0000
SDM_SEL[1:0] = 00
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 1010
INSEL[3:0] = 0000
SDM_SEL[1:0] = 00
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 0010
INSEL[3:0] = 0000
SDM_SEL[1:0] = 00
PRIM_MODE[3:0] = 0001
VID_STD[3:0] = 1100
ADC_SW_MAN_EN, manual input muxing enable,
IO map, Address C4[7]
ADC0_SW[3:0], ADC0 mux configuration, IO map,
Address C3[3:0]
ADC1_SW[3:0], ADC1 mux configuration, IO map,
Address C3[7:4]
ADC2_SW[3:0], ADC2 mux configuration, IO map,
Address C4[3:0]
ADC3_SW[3:0], ADC3 mux configuration, IO map,
Address F3[7:4]
1
ADC2
Connection ADC3_SW_SEL[3:0]
N/A
A
A
A
A
N/A
IN
IN
IN
IN
2
4
5
6
0001
0010
0100
0101
0110
1100
ADC3
Connection
N/A
N/A
A
N/A
N/A
N/A
IN
4