ADV7181CBCPZ Analog Devices Inc, ADV7181CBCPZ Datasheet - Page 14

• Manufacturer Part Number: ADV7181CBCPZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7181CBCPZ

• Adc/dac Resolution: 10b
• Screening Level: Industrial
• Package Type: LFCSP EP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

ADV7181C
DETAILED DESCRIPTION
ANALOG FRONT END
The ADV7181C analog front end comprises four 10-bit ADCs
that digitize the analog video signal before applying it to the SDP
or CP. The analog front end uses differential channels to each
ADC to ensure high performance in a mixed-signal application.
The front end also includes a 6-channel input mux that enables
multiple video signals to be applied to the ADV7181C. Current
and voltage clamps are positioned in front of each ADC to ensure
that the video signal remains within the range of the converter.
Fine clamping of the video signals is performed downstream by
digital fine clamping in either the CP or SDP.
Optional antialiasing filters are positioned in front of each ADC.
These filters can be used to band-limit standard definition
video signals, removing spurious out-of-band noise.
The ADCs are configured to run in 4× oversampling mode
when decoding composite and S-Video inputs; 2× oversampling
is performed for component 525i, 625i, 525p, and 625p sources.
All other video standards are 1× oversampled. Oversampling
the video signals reduces the cost and complexity of external
antialiasing filters with the benefit of an increased signal-to-
noise ratio (SNR).
The ADV7181C can support simultaneous processing of CVBS
and RGB standard definition signals to enable SCART compati-
bility and overlay functionality. A combination of CVBS and
RGB inputs can be mixed and output under the control of the
I
STANDARD DEFINITION PROCESSOR (SDP)
The SDP section is capable of decoding a large selection of
baseband video signals in composite, S-Video, and YUV
formats. The video standards supported by the SDP include
PAL B/D/I/G/H, PAL60, PAL M, PAL N, NTSC M/J, NTSC 4.43,
and SECAM B/D/G/K/L. The ADV7181C automatically detects
the video standard and processes it accordingly.
The SDP has a 5-line super adaptive 2D comb filter that gives
superior chrominance and luminance separation when decoding a
composite video signal. This highly adaptive filter automatically
adjusts its processing mode according to video standards and
signal quality with no user intervention required. The SDP has
an IF filter block that compensates for attenuation in the high
frequency luma spectrum due to the tuner SAW filter.
The SDP has specific luminance and chrominance parameter
control for brightness, contrast, saturation, and hue.
The ADV7181C implements a patented ADLLT algorithm to
track varying video line lengths from sources such as a VCR.
ADLLT enables the ADV7181C to track and decode poor
quality video sources such as VCRs, noisy sources from tuner
2
C registers and the fast blank pin.
Rev. C | Page 14 of 20
outputs, VCD players, and camcorders. The SDP also contains a
chroma transient improvement (CTI) processor. This processor
increases the edge rate on chroma transitions, resulting in a
sharper video image.
The SDP can process a variety of VBI data services, such as
teletext, closed captioning (CC), wide screen signaling (WSS),
video programming system (VPS), vertical interval time codes
(VITC), copy generation management system (CGMS), GemStar
1×/2×, and extended data service (XDS). The ADV7181C SDP
section has a Macrovision 7.1 detection circuit that allows it
to detect Type I, Type II, and Type III protection levels. The
decoder is also fully robust to all Macrovision signal inputs.
COMPONENT PROCESSOR (CP)
The CP section is capable of decoding/digitizing a wide range of
component video formats in any color space. Component video
standards supported by the CP are 525i, 625i, 525p, 625p, 720p,
1080i, graphics up to XGA at 70 Hz, and many other standards.
The CP section of the ADV7181C contains an AGC block.
When no embedded synchronization is present, the video
gain can be set manually. The AGC section is followed by a
digital clamp circuit that ensures the video signal is clamped to
the correct blanking level. Automatic adjustments within the
CP include gain (contrast) and offset (brightness); manual
adjustment controls are also supported.
A fixed mode graphics RGB to component output is available.
A color space conversion matrix is placed between the analog
front end and the CP section. This enables YPrPb-to-DDR RGB
and RGB-to-YCrCb conversions. Many other standards of color
space can be implemented using the color space converter.
The output section of the CP is highly flexible. It can be confi-
gured in SDR mode with one data packet per clock cycle or in
a DDR mode where data is presented on the rising and falling
edges of the clock. In SDR mode, a 20-bit 4:2:2 is possible. In
these modes, HS/CS, VS, and FIELD/DE (where applicable)
timing reference signals are provided. In DDR mode, the
ADV7181C can be configured in an 8-bit 4:2:2 YCrCb or
12-bit 4:4:4 RGB pixel output interface with corresponding
timing signals.
The CP section contains circuitry to enable the detection of
Macrovision encoded YPrPb signals for 525i, 625i, 525p, and
625p. It is designed to be fully robust when decoding these
types of signals.
VBI extraction of component data is performed by the CP
section of the ADV7181C for interlaced, progressive, and high
definition scanning rates. The data extracted can be read back
over the I
2
C interface.