935274109557 NXP Semiconductors, 935274109557 Datasheet - Page 35

• Manufacturer Part Number: 935274109557
• Manufacturer: NXP Semiconductors

Specifications of 935274109557

• Screening Level: Commercial
• Package Type: SQFP
• Pin Count: 208
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
7.9.4
An auto-switch mode is available if Clock mode 2 is
selected. In this event the PLL will switch to Clock mode 1
or 3 if the conditions for Clock mode 2 are no longer met
(i.e. video frame frequency outside the range
1 200
I
If auto-switch occurs then a host interrupt can be flagged.
7.9.5
It is possible to tune the crystal frequency by up to
1 200
used to achieve the MPEG-2 accuracy of 1 20
standard crystals.
7.9.6
It is possible to use an external system clock. For start-up
before switching to the external clock input a crystal has to
be connected or the external frequency has to be applied
to pin XTALI. The input voltage for this pin must be limited
to 2.5 V. An external clock source cannot be used with
Clock mode 2.
7.9.7
A switchable sampling frequency for an audio
Analog-to-Digital Converter (ADC) is generated by the
internal PLL. Two sampling frequencies are selectable:
256
used as clock signal for an external audio ADC. The
system clock reference frequency as described in Table 9,
is used as reference for the internal PLL generating the
audio clock.
7.10
7.10.1
An external reset pulse at power-up is needed to start-up
the SAA6752HS. This will start the oscillator and initialize
hardware and firmware. The SAA6752HS can be set to a
power saving sleep mode where all internal clocks are
switched off. In this mode restarting can only be done by a
hard reset pulse.
2004 Jan 26
2
C-bus command during the SAA6752HS initialization.
MPEG-2 video and MPEG-audio/AC-3
audio encoder with multiplexer
48 kHz and 384
Power control and reset
C
C
E
A
G
10
10
XTERNAL CLOCK SOURCE
UDIO CLOCK
LOCK MODE
RYSTAL TUNING
ENERAL
6
6
). The auto-switch preference is set by an
via the I
2
2
C-bus. If necessary this can be
AUTO
48 kHz. This clock output can be
-
SWITCH
10
6
with
35
7.11
7.11.1
The I
transceiver. It is used for all control settings. The read
mode may be used to read back error or status codes.
The I
at 100 kHz and 400 kHz clock frequency and suitable for
bus line voltage levels of 3.3 V. If an I
voltage is used by an application, it is possible to add a
small interface between 3.3 V and a higher voltage level.
Only two MOSFET transistors (e.g. BSN10, BSN20 or
BSS83) are needed. A description of this circuit is
available at
http://www.semiconductors.philips.com/i2c/facts/
Information about the I
brochure “The I
(order number 9398 393 40011).
7.11.2
Two write I
40H and 42H (8-bit), dependent on the state of address
select pin I2CADDRSEL. This avoids possible address
conflict of addresses with other devices. A HIGH-level at
the address selection pin will set the device write address
to 42H.
Similarly for read operations there are two slave
addresses: 41H and 43H. A HIGH-level at the address
selection pin will set the device read address to 43H.
7.12
7.12.1
The SAA6752HS is capable of flagging certain events to a
host via a host interrupt flag pin H_IRF. The host is able to
read back a 16-bit status word via the I
the specific event and take action accordingly. Detectable
events include copyright violations, loss of input
synchronization, DVD compliance errors etc.
7.12.2
A list of the SAA6752HS exception conditions, as
indicated by the status word, is defined in Table 11. The
I
2
C-bus subaddress is 12H (see Table 14).
2
2
C-bus interface is compliant to the I
C-bus interface within the SAA6752HS is a slave
I
Exception handling
2
C-bus interface
G
S
G
E
LAVE
XCEPTION CONDITIONS
ENERAL
ENERAL
2
C-bus slave addresses (SAD) are available,
2
A
C-bus and how to use it”
DDRESSES
2
C-bus can be found in the
SAA6752HS
Product specification
2
C-bus with higher
2
C-bus to identify
2
C-bus standard