ADV7170KSUZ Analog Devices Inc, ADV7170KSUZ Datasheet - Page 49

• Manufacturer Part Number: ADV7170KSUZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7170KSUZ

• Adc/dac Resolution: 10b
• Screening Level: Industrial
• Package Type: TQFP
• Pin Count: 44
• Lead Free Status / RoHS Status: Compliant

APPENDIX 9—RECOMMENDED REGISTER VALUES
The ADV7170/ADV7171 registers can be set depending on the
user standard required.
The following examples give the various register formats for
several video standards.
In each case, the output is set to composite o/p with all DACs
powered up and with the BLANK input control disabled.
Additionally, the burst and color information are enabled on the
Table 13. PAL B/D/G/H/I (F
Address
00Hex
01Hex
02Hex
03Hex
04Hex
07Hex
08Hex
09Hex
0AHex
0BHex
0CHex
0DHex
0EHex
0FHex
10Hex
11Hex
12Hex
13Hex
14Hex
15Hex
16Hex
17Hex
18Hex
19Hex
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Timing Register 0
Timing Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
CGMS_WSS Register 0
CGMS_WSS Register 1
CGMS_WSS Register 2
Teletext Request Control Register
SC
= 4.43361875 MHz)
Data
05Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
CBHex
8AHex
09Hex
2AHex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
Rev. C | Page 49 of 64
output and the internal color bar generator is switched off. In
the examples shown, the timing mode is set to Mode 0 in slave
format. TR02 to TR00 of the Timing Register 0 control the
timing modes. For a detailed explanation of each bit in the
command registers, please see the
section. TR07 should be toggled after setting up a new timing
mode. Timing Register 1 provides additional control over the
position and duration of the timing signals. In the examples,
this register is programmed in default mode.
Table 14. PAL M (F
Address
00Hex
01Hex
02Hex
03Hex
04Hex
07Hex
08Hex
09Hex
0AHex
0BHex
0CHex
0DHex
0EHex
0FHex
10Hex
11Hex
12Hex
13Hex
14Hex
15Hex
16Hex
17Hex
18Hex
19Hex
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Timing Register 0
Timing Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 3
Subcarrier Phase Register
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
CGMS_WSS Register 0
CGMS_WSS Register 1
CGMS_WSS Register 2
Teletext Request Control Register
Subcarrier Frequency Register 2
SC
= 3.57561149 MHz)
Register Programming
ADV7170/ADV7171
Data
02Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
A3Hex
EFHex
E6Hex
21Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex