ADV7170KSUZ Analog Devices Inc, ADV7170KSUZ Datasheet - Page 30

• Manufacturer Part Number: ADV7170KSUZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7170KSUZ

• Adc/dac Resolution: 10b
• Screening Level: Industrial
• Package Type: TQFP
• Pin Count: 44
• Lead Free Status / RoHS Status: Compliant

ADV7170/ADV7171
MODE REGISTER 1 MR1 (MR17 TO MR10)
(Address (SR4 to SR0) = 01H)
Figure 39 shows the various operations under the control of
Mode Register 1. This register can be read from as well as
written to.
MR1 BIT DESCRIPTION
Interlace Control (MR10)
This bit is used to set up the output to interlaced or noninter-
laced mode. This mode is only relevant when the part is in
composite video mode.
Closed Captioning Field Selection (MR12 to MR11)
These bits control the fields on which closed captioning data is
displayed. Closed captioning information can be displayed on
an odd field, even field, or both odd and even fields.
DAC Control (MR16 to MR13)
These bits can be used to power down the DACs. This can be
used to reduce the power consumption of the ADV7170/
ADV7171 if any of the DACs are not required in the
application.
MR07
0
0
0
0
1
1
1
1
MR06
0
0
1
1
0
0
1
1
MR07
CHROMA FILTER SELECT
MR05
0
1
0
1
0
1
0
1
MR06
1.3MHz LOW PASS FILTER
0.65MHz LOW PASS FILTER
1.0MHz LOW PASS FILTER
2.0MHz LOW PASS FILTER
RESERVED
CIF
Q CIF
RESERVED
MR05
Figure 38. Mode Register 0
Rev. C | Page 30 of 64
MR04
MR04
MR03
0
0
0
0
1
1
1
1
Color Bar Control (MR17)
This bit can be used to generate and output an internal color bar
test pattern. The color bar configuration is 100/7.5/75/7.5 for
NTSC and 100/0/75/0 for PAL. It is important to note that when
color bars are enabled, the ADV7170/ADV7171 are configured
in a master timing mode.
MODE REGISTER 2 MR2 (MR27 TO MR20)
(Address [SR4 to SR0] = 02H)
Mode Register 2 is an 8-bit-wide register.
Figure 40 shows the various operations under the control of
Mode Register 2. This register can be read from as well as
written to.
MR2 BIT DESCRIPTION
Square Pixel Control (MR20)
This bit is used to set up square pixel mode. This is available in
slave mode only. For NTSC, a 24.5454 MHz clock must be
supplied. For PAL, a 29.5 MHz clock must be supplied.
MR03
0
0
1
0
0
0
1
1
MR02
LUMA FILTER SELECT
MR01
MR02
0
0
1
1
0
1
0
1
0
1
0
1
STANDARD SELECTION
MR01
MR00
OUTPUT VIDEO
LOW PASS FILTER (NTSC)
LOW PASS FILTER (PAL)
NOTCH FILTER (NTSC)
NOTCH FILTER (PAL)
EXTENDED MODE
CIF
Q CIF
RESERVED
0
1
0
1
NTSC
PAL (B, D, G, H, I)
PAL (M)
RESERVED
MR00