ADV7174KCPZ Analog Devices Inc, ADV7174KCPZ Datasheet - Page 50

• Manufacturer Part Number: ADV7174KCPZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7174KCPZ

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LFCSP EP
• Pin Count: 40
• Lead Free Status / RoHS Status: Compliant

ADV7174/ADV7179
APPENDIX 8—RECOMMENDED REGISTER VALUES
The ADV7174/ADV7179 registers can be set depending on the
user standard required. The power-on reset values can be found
in Figure 37.
The following examples give the various register formats for
several video standards. In each case, the output is set to compos-
ite output with all DACs powered up and with the input control
disabled. Additionally, the burst and BLANK color information
is enabled on the output, and the internal color bar generator is
Table 24. PAL B/D/G/H/I (F
Address
00H
01H
02H
03H
04H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
Description
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Timing Register 0
Timing Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
CGMS_WSS Register 0
CGMS_WSS Register 1
CGMS_WSS Register 2
Telext Request Control Register
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
CGMS_WSS Register 0
CGMS_WSS Register 1
CGMS_WSS Register 2
Teletext Request Control Register
SC
= 4.43361875 MHz)
Data
05H
10H
00H
00H
00H
00H
00H
CBH
8AH
09H
2AH
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
Rev. B | Page 50 of 52
switched off. In the examples shown, the timing mode is set to
Mode 0 in slave format. TR02–TR00 of the Timing Register 0
control the timing modes. For a detailed explanation of each bit
in the command registers, refer to the
section. TR07 should be toggled after setting up a new timing
mode. Timing Register 1 provides additional control over the
position and duration of the timing signals. In the examples,
this register is programmed in default mode.
Table 25. PAL N (F
Address
00H
01H
02H
03H
04H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
Description
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Timing Register 0
Timing Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
CGMS_WSS Register 0
CGMS_WSS Register 1
CGMS_WSS Register 2
Teletext Request Control Register
SC
= 4.43361875 MHz)
Register Programming
00H
00H
00H
Data
05H
10H
00H
00H
00H
CBH
8AH
09H
2AH
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H