STULPI01ATBR STMicroelectronics, STULPI01ATBR Datasheet - Page 22

• Manufacturer Part Number: STULPI01ATBR
• Manufacturer: STMicroelectronics

Specifications of STULPI01ATBR

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Operating Supply Voltage (typ): Not RequiredV
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): Not RequiredV
• Operating Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant

Block description
Table 10.
Note:
6.15
22/44
Default car kit signals mapping (UART_DIR = 0)
Car kit signals mapping (UART_DIR = 1)
reserved
reserved
Signal
Signal
RXD
RXD
TXD
TXD
INT
INT
Car kit signals mapping
TXD or RXD paths are activated only when corresponding bits TXD_EN/RXD_EN in car kit
Control Register bits
UART_2V7 bit controls the voltage level of UART signaling. In case 2V7 volt signaling is
used, after the UART mode is entered, PLL is disabled and the voltage on the regulator
output starts to decrease to 2.7 V. After time marked as t
bus is enabled.
When leaving car kit mode, TXD is disabled immediately when STP pin is asserted. The
time required to exit car kit mode is equivalent to the time needed for PLL startup.
When 3.3 volt UART signaling is selected, TXD line is enabled immediately after entering
car kit mode, and disabled after exit from this mode.
When car kit mode is used with 2V7 signaling, PLL and output clock is always stopped
regardless on the setting of ClockSuspendM bit.
Low-power mode
STULPI01 enters low-power mode when SuspendM bit in interface control register is set to
0b. Most of the references are turned off, PLL and clock are turned off, but the full wake-up
capability as defined in the ULPI specification is still maintained.
When in low-power mode, the PHY drives D3-D0 with the signals listed in table below. Line
state is driven combinatorially from the SE receivers. The INT signal is asserted whenever
any unmasked interrupt occurs. The PHY latches interrupt events directly from analog
circuitry because the clock is powered down.
DATA[2] (input)
DATA[0] (input)
DATA[2] (input)
DATA[0] (input)
DATA[1] (output) <-
DATA[3] (output)
DATA[1] (output) <-
DATA[3] (output)
(Table
23) are set.
->
->
ULPI lines
ULPI lines
Doc ID 14817 Rev 3
UARTON2V7
DP (output)
DM (input)
STULPI01A - STULPI01B
the TXD output on USB
DM (output)
DP (input)
USB lines
USB lines