ISP1301BS,118 NXP Semiconductors, ISP1301BS,118 Datasheet - Page 46

• Manufacturer Part Number: ISP1301BS,118
• Manufacturer: NXP Semiconductors

Specifications of ISP1301BS,118

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Operating Supply Voltage (typ): Not RequiredV
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): Not RequiredV
• Operating Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant

23. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10. Clock wake-up by ID change (1) . . . . . . . . . . . . .26
Fig 11. Clock wake-up by ID change (2) . . . . . . . . . . . . .26
Fig 12. Clock wake-up by data line SRP . . . . . . . . . . . . .26
Fig 13. Writing data to the ISP1301 registers . . . . . . . . .29
Fig 14. Current address read . . . . . . . . . . . . . . . . . . . . . .30
Fig 15. Random address read . . . . . . . . . . . . . . . . . . . . .31
Fig 16. Rise time and fall time . . . . . . . . . . . . . . . . . . . . .37
Fig 17. Timing of DAT/VP and SE0/VM to DP and DM . .37
Fig 18. Timing of OE_N/INT_N to DP and DM . . . . . . . .37
Fig 19. Timing of DP and DM to RCV, VP or DAT/VP and
Fig 20. SIE interface bus turnaround timing . . . . . . . . . .38
Fig 21. Load on pins DP and DM. . . . . . . . . . . . . . . . . . .38
Fig 22. Load on pins DP and DM for enable time and
Fig 23. Load on pins VM, SE0/VM, VP, DAT/VP
Fig 24. Definition of timing for standard-mode devices on
Fig 25. Application diagram for the OTG Controller with the
Fig 26. Application diagram for the OTG Controller with the
Fig 27. Package outline SOT616-1 (HVQFN24) . . . . . . .42
ISP1301_5
Product data sheet
VM or SE0/VM . . . . . . . . . . . . . . . . . . . . . . . . . . .37
disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
and RCV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
the I
DAT_SE0 SIE interface . . . . . . . . . . . . . . . . . . . .40
VP_VM SIE interface . . . . . . . . . . . . . . . . . . . . . .41
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin configuration HVQFN24 (top view) . . . . . . . . .4
Pin configuration HVQFN24 (bottom view) . . . . . .4
Internal POR timing . . . . . . . . . . . . . . . . . . . . . . . .9
Using external charge pump . . . . . . . . . . . . . . . .10
Charge pump capacitor . . . . . . . . . . . . . . . . . . . . 11
Clock stopped using the GLOBAL_PWR_DN bit.25
Clock wake-up using SCL . . . . . . . . . . . . . . . . . .25
Clock wake-up by V
2
C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
BUS
. . . . . . . . . . . . . . . . . . . .26
Rev. 05 — 2 September 2009
USB OTG transceiver
© ST-ERICSSON 2009. All rights reserved.
ISP1301
46 of 49