ISP1507DBSUM STEricsson, ISP1507DBSUM Datasheet - Page 46

• Manufacturer Part Number: ISP1507DBSUM
• Manufacturer: STEricsson

Specifications of ISP1507DBSUM

• Lead Free Status / RoHS Status: Compliant

Table 24.
Table 25.
CD00222690
Product data sheet
Bit
7
6
5
4 to 3
2
1 to 0
Bit
Symbol
Reset
Access
Symbol
-
SUSPENDM
RESET
OPMODE[1:0]
TERMSELECT
XCVRSELECT[1:0]
FUNC_CTRL - Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit
description
INTF_CTRL - Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit allocation
PROT_DIS
10.1.3 INTF_CTRL register
R/W/S/C
INTF_
7
0
The INTF_CTRL register enables alternative interfaces. All of these modes are optional
features provided for legacy link cores. Setting more than one of these fields results in
undefined behavior.
IND_PASS
R/W/S/C
Description
reserved
Suspend LOW: Active LOW PHY suspend.
Places the PHY into low-power mode. The PHY will power down all blocks, except the
full-speed receiver, OTG comparators and ULPI pins.
To come out of low-power mode, the link must assert STP. The PHY will automatically clear
this bit when it exits low-power mode.
0b — Low-power mode
1b — Powered (default)
Reset: Active HIGH transceiver reset.
After the link sets this bit, the PHY will assert DIR and reset the digital core. This does not
reset the ULPI interface or the ULPI register set.
When reset is completed, the PHY will deassert DIR and automatically clear this bit, followed
by an RXCMD update to the link.
0b — Do not reset (default)
1b — Reset
The link must wait for DIR to deassert before using the ULPI bus. Does not reset the ULPI
interface or the ULPI register set.
Operation Mode: Selects the required bit-encoding style during transmit.
00b — Normal operation (default)
01b — Non-driving
10b — Disable bit-stuffing and NRZI encoding
11b — Do not automatically add SYNC and EOP when transmitting; must be used only for
high-speed packets
Termination Select: Controls the internal 1.5 kΩ full-speed pull-up resistor and 45 Ω
high-speed terminations. Control over bus resistors changes, depending on
XCVRSELECT[1:0], OPMODE[1:0], DP_PULLDOWN and DM_PULLDOWN, as shown in
Table
Transceiver Select: Selects the required transceiver speed.
00b — Enable the high-speed transceiver
01b — Enable the full-speed transceiver
10b — Enable the low-speed transceiver
11b — Enable the full-speed transceiver for low-speed packets (full-speed preamble is
automatically prefixed)
THRU
6
0
7.
R/W/S/C
COMPL
IND_
5
0
Table 25
Rev. 04 — 20 May 2010
reserved
R/W/S/C
provides the bit allocation of the register.
4
0
SUSPENDM
ULPI HS USB host and peripheral transceiver
CLOCK_
R/W/S/C
3
0
ISP1507C; ISP1507D
reserved
R/W/S/C
2
0
3PIN_FSLS
_SERIAL
R/W/S/C
© ST-ERICSSON 2010. All rights reserved.
1
0
6PIN_FSLS
_SERIAL
R/W/S/C
0
0
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