ISP1504ABS,118 NXP Semiconductors, ISP1504ABS,118 Datasheet - Page 50

• Manufacturer Part Number: ISP1504ABS,118
• Description: RF Transceiver USB ULPI TRANSCEIVER
• Manufacturer: NXP Semiconductors

Specifications of ISP1504ABS,118

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Operating Supply Voltage (typ): Not RequiredV
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): Not RequiredV
• Operating Supply Voltage (min): Not RequiredV
• Pin Count: 32
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Supply Voltage: 1.65 V to 3.6 V
• Mounting Style: SMD/SMT
• Package / Case: HVQFN-32
• Lead Free Status / RoHS Status: Compliant
• Other names: 935278308118 ISP1504ABS-T

NXP Semiconductors
Table 26.
Table 27.
ISP1504A_ISP1504C_3
Product data sheet
Bit
7
6
5
4 to 3
2
1 to 0
Bit
Symbol
Reset
Access
Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit description
Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit allocation
Symbol
-
SUSPENDM
RESET
OPMODE[1:0]
TERMSELECT Termination Select: Controls the internal 1.5 k full-speed pull-up resistor and 45
XCVRSELECT
[1:0]
PROT_DIS
10.1.3 Interface Control register
R/W/S/C
INTF_
7
0
The Interface Control register enables alternative interfaces. All of these modes are
optional features provided for legacy link cores. Setting more than one of these fields
results in undefined behavior.
IND_PASS
R/W/S/C
Description
reserved
Suspend LOW: Active LOW PHY suspend.
Places the PHY into low-power mode. The PHY will power down all blocks, except the
full-speed receiver, OTG comparators and ULPI interface pins.
To come out of low-power mode, the link must assert STP. The PHY will automatically clear
this bit when it exits low-power mode.
0b — Low-power mode
1b — Powered (default)
Reset: Active HIGH transceiver reset.
After the link sets this bit, the PHY will assert DIR and reset the digital core. This does not
reset the ULPI interface or the ULPI register set.
When reset is completed, the PHY will deassert DIR and automatically clear this bit, followed
by an RXCMD update to the link.
0b — Do not reset (default)
1b — Reset
The link must wait for DIR to deassert before using the ULPI bus. Does not reset the ULPI
interface or the ULPI register set.
Operation Mode: Selects the required bit-encoding style during transmit.
00b — Normal operation (default)
01b — Non-driving
10b — Disable bit-stuffing and NRZI encoding
11b — Do not automatically add SYNC and EOP when transmitting; must be used only for
high-speed packets
high-speed terminations. Control over bus resistors changes, depending on
XCVRSELECT[1:0], OPMODE[1:0], DP_PULLDOWN and DM_PULLDOWN, as shown in
Table
Transceiver Select: Selects the required transceiver speed.
00b — Enable the high-speed transceiver
01b — Enable the full-speed transceiver (default)
10b — Enable the low-speed transceiver
11b — Enable the full-speed transceiver for low-speed packets (full-speed preamble is
automatically prefixed)
THRU
6
0
8.
R/W/S/C
COMPL
IND_
5
0
Rev. 03 — 7 April 2008
reserved
R/W/S/C
Table 27
4
0
provides the bit allocation of the register.
SUSPENDM
CLOCK_
R/W/S/C
ISP1504A; ISP1504C
3
0
reserved
R/W/S/C
ULPI HS USB OTG transceiver
2
0
3PIN_FSLS
_SERIAL
R/W/S/C
1
0
© NXP B.V. 2008. All rights reserved.
6PIN_FSLS
_SERIAL
R/W/S/C
0
0
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