ISP1507CBS STEricsson, ISP1507CBS Datasheet - Page 28

• Manufacturer Part Number: ISP1507CBS
• Manufacturer: STEricsson

Specifications of ISP1507CBS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
ISP1507C_ISP1507D_1
Product data sheet
Fig 8.
DATA[7:0]
CLOCK
NXT
STP
DIR
AD indicates the address byte, and D indicates the data byte.
Example of register write, register read, extended register write and extended register read
9.6 Register read and write operations
9.7 USB reset and high-speed detection handshake (chirp)
(REGW)
register write
TXCMD
immediate
enable HostDisconnect by setting the HOST_DISCON_R and HOST_DISCON_F bits in
the USB_INTR_EN_R_E and USB_INTR_EN_F_E registers, respectively. Changes in
HostDisconnect will cause the PHY to send an RXCMD to the link with the updated value.
Figure 8
addressing and extended addressing register operations. Extended register addressing is
optional for links. Note that register operations will be aborted if the ISP1507 unexpectedly
asserts DIR during the operation. When a register operation is aborted, the link must retry
until successful. For more information on register operations, refer to UTMI+ Low Pin
Interface (ULPI) Specification Rev. 1.1 .
Figure 9
handshake (chirp). The sequence is shown for hosts and peripherals.
show all RXCMD updates and timing is not to scale. The sequence is as follows:
1. USB reset: The host detects a peripheral attachment as low-speed if DM is HIGH and
D
as full-speed if DP is HIGH. If a host detects a full-speed peripheral, it resets the
peripheral by writing to the Function Control register (see
XCVRSELECT[1:0] = 00b (high-speed) and TERMSELECT = 0b are then set which
drives SE0 on the bus (DP and DM connected to ground through 45 ). The host also
sets OPMODE[1:0] = 10b for correct chirp transmit and receive. The start of SE0 is
labeled T
Remark: To receive chirp signaling, the host must also consider the high-speed
differential receiver output. The host controller must interpret LINESTATE[1:0] as
shown in
shows register read and write sequences. The ISP1507 supports immediate
shows the sequence of events for USB reset and high-speed detection
TXCMD
(EXTW) AD D
register write
0
Table
extended
.
11.
Rev. 01 — 28 May 2008
TXCMD
(REGR)
register read
immediate
D
ULPI HS USB host and peripheral transceiver
ISP1507C; ISP1507D
TXCMD
(EXTW)
register read
extended
AD
D
Section
Figure 9
10.1.2).
© NXP B.V. 2008. All rights reserved.
004aaa710
does not
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