SC16C550IN40 NXP Semiconductors, SC16C550IN40 Datasheet - Page 10

• Manufacturer Part Number: SC16C550IN40
• Manufacturer: NXP Semiconductors

Specifications of SC16C550IN40

• Transmit Fifo: 16Byte
• Receive Fifo: 16Byte
• Transmitter And Receiver Fifo Counter: Yes
• Package Type: PDIP
• Operating Supply Voltage (max): 5.5V
• Mounting: Through Hole
• Pin Count: 40
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
9397 750 11619
Product data
6.1 Internal registers
6.2 FIFO operation
The SC16C550 provides 15 internal registers for monitoring and control. These
registers are shown in
in the standard 16C550. These registers function as data holding registers
(THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register
(FCR), line status and control registers (LCR/LSR), modem status and control
registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM),
and a user accessible scratchpad register (SPR). Beyond the general 16C550
features and capabilities, the SC16C550 offers an enhanced feature register set
(EFR, Xon/Xoff1-2) that provides on-board hardware/software flow control. Register
functions are more fully described in the following paragraphs.
Table 3:
[1]
[2]
[3]
The 16-byte transmit and receive data FIFOs are enabled by the FIFO Control
Register bit-0 (FCR[0]). With 16C550 devices, the user can set the receive trigger
level, but not the transmit trigger level. The receiver FIFO section includes a time-out
function to ensure data is delivered to the external CPU. An interrupt is generated
whenever the Receive Holding Register (RHR) has not been read following the
loading of a character or the receive trigger level has not been reached.
A2
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR/LSR, SPR)
0
0
0
0
1
1
1
1
Baud rate register set (DLL/DLM)
0
0
Enhanced register set (EFR, Xon/off 1-2)
0
1
1
1
1
These registers are accessible only when LCR[7] is a logic 0.
These registers are accessible only when LCR[7] is a logic 1.
Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to
“BF(HEX).
A1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
Internal registers decoding
A0
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
Rev. 05 — 19 June 2003
READ mode
Receive Holding Register
Interrupt Status Register
Line Status Register
Modem Status Register
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
Enhanced Feature Register
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
Table
3. Twelve registers are similar to those already available
UART with 16-byte FIFO and IrDA encoder/decoder
[2]
[3]
WRITE mode
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
n/a
n/a
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
Enhanced Feature Register
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC16C550
[1]
10 of 52