SC16C850VIBS-S NXP Semiconductors, SC16C850VIBS-S Datasheet - Page 22

• Manufacturer Part Number: SC16C850VIBS-S
• Manufacturer: NXP Semiconductors

Specifications of SC16C850VIBS-S

• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Mounting: Surface Mount
• Pin Count: 32
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SC16C850V
Product data sheet
7.3.1 FIFO mode
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs and set the receive FIFO trigger
levels.
Table 9.
[1]
[2]
Table 10.
[1]
Bit
7:6
5:4
3
2
1
0
FCR[7]
0
0
1
1
For 128-byte FIFO mode, refer to
For 128-byte FIFO mode, refer to
When RXINTLVL or TXINTLVL or FLWCNTH or FLWCNTL contains any value other than 0x00, receive and
transmit trigger levels are set by RXINTLVL, TXINTLVL; see
FCR[7:6]
FCR[5:4]
FCR[3]
FCR[2]
FCR[1]
FCR[0]
Symbol
FIFO Control Register bits description
RCVR trigger levels
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
FCR[6]
0
1
0
1
All information provided in this document is subject to legal disclaimers.
Description
Receive trigger level in 32-byte FIFO mode.
These bits are used to set the trigger level for receive FIFO interrupt and flow
control. The SC16C850V will issue a receive ready interrupt when the number
of characters in the receive FIFO reaches the selected trigger level. Refer to
Table
Transmit trigger level in 32-byte FIFO mode.
These bits are used to set the trigger level for the transmit FIFO interrupt and
flow control. The SC16C850V will issue a transmit empty interrupt when the
number of characters in FIFO drops below the selected trigger level. Refer to
Table
reserved
XMIT FIFO reset.
RCVR FIFO reset.
FIFO enable.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic. This bit will return to a logic 0 after clearing the FIFO.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic. This bit will return to a logic 0 after clearing the FIFO.
logic 0 = disable the transmit and receive FIFO (normal default condition)
logic 1 = enable the transmit and receive FIFO
Rev. 5 — 19 January 2011
10.
11.
RX FIFO trigger level in 32-byte FIFO mode
8 bytes
16 bytes
24 bytes
28 bytes
Section
Section
7.16,
7.15,
Section
Section
7.17,
7.17,
Section 6.4 “FIFO
Section
Section
[1]
[2]
7.18.
7.18.
SC16C850V
operation”.
[1]
© NXP B.V. 2011. All rights reserved.
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