STCCP27TBR STMicroelectronics, STCCP27TBR Datasheet
STCCP27TBR
Specifications of STCCP27TBR
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STCCP27TBR Summary of contents
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High speed dual differential line receivers, Feature summary SUB-Low voltage differential signaling inputs 100mV with R = 100 , High signaling rate 416MHz max (D+,D-, CLK+, CLK 52MHz max ...
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Contents 1 Schematic diagram 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STCCP27A 1 Schematic diagram Figure 1. Simplified application block diagram Figure 2. Block diagram Schematic diagram 3/19 ...
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Schematic diagram 2 Figure 3. Simplified I C line block diagram 4/19 STCCP27A ...
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STCCP27A 2 Pin configuration Figure 4. Pin configuration (top through view - bumps are on the other side) Table 1. Pin description Pin n° A2 ...
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Pin configuration Table 2. Main function table Input Enable SYNC_SEL SOF ( EOF( SOL( EOL( High ...
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STCCP27A 3 Maximum ratings Table 4. Absolute maximum ratings Symbol V Main supply voltage DD V Secondary supply voltage L V SubLVDS data bus input voltage (D+, D SubLVDS clock bus input voltage (CLK+, CLK-) CLK V DC ...
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Electrical characteristics 4 Electrical characteristics Table 6. Electrical characteristics (Over recommended operating conditions unless otherwise noted. All typical values are at T Symbol Parameter Common mode input V CM voltage (see fig.1) Input leakage current I I (D+, D-, CLK1+, ...
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STCCP27A Table 7. Switching characteristics (R operating conditions unless otherwise noted. Typical values are referred to T 25°C and V Symbol Parameter Rise time LVTTL Output voltage t r (10% to 90%) Fall time LVTTL output voltage t f (90% ...
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Timing diagram 5 Timing diagram (unless otherwise specified T Figure SUD-CLK , HCLK-D Figure 7. Bit order in synchronization codes and data, LSB first (example start of frame), image frame structure Note: LSB (bytewise Least Significant Bit ...
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STCCP27A Figure 8. Disabled sync mode free running clock IN (SYNC_SEL=GND) (D1-D8 will get out input data DIN, including sync code) Timing diagram 11/19 ...
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Timing diagram Figure 9. Enabled sync mode free running clock IN (SYNC_SEL=V data DIN only, excluding sync code) 12/19 STCCP27A ) (D1-D8 will get out input DD ...
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STCCP27A Figure 10. Enabled sync mode gated clock IN (SYNC_SEL=VDD) (D1-D8 will get out input data DIN only, excluding sync code) Timing diagram 13/19 ...
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Timing diagram Figure 11. Enabled sync mode free running clock IN (SYNC_SEL=V data DIN only, excluding sync code Figure 12. Disabled sync mode free running clock IN (SYNC_SEL=Gnd) (D1-D8 will get out input data DIN only, excluding sync code) 14/19 ...
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STCCP27A 6 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the ...
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Package mechanical data DIM. MIN 0.78 b 0. 16/19 TFBGA25 MECHANICAL DATA mm. TYP MAX. 1.1 1.16 0.25 0.86 0.30 0.35 3.0 3.1 2 3.0 3.1 2 0.5 ...
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STCCP27A Tape & Reel TFBGA25 MECHANICAL DATA DIM. MIN 12 3.9 P 7.9 mm. TYP MAX. MIN. 330 13.2 0.504 0.795 2.362 14.4 3.3 3.3 1.60 4.1 0.153 8.1 ...
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Revision history 7 Revision history Table 9. Revision history Date Revision 12-Apr-2006 1 18/19 Initial release. STCCP27A Changes ...
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... STCCP27A Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...