DP83934CVUL20 National Semiconductor, DP83934CVUL20 Datasheet - Page 45

• Manufacturer Part Number: DP83934CVUL20
• Manufacturer: National Semiconductor

Specifications of DP83934CVUL20

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

6 0 SONIC-T Registers
6 3 4 Transmit Control Register (Continued)
Bit
9
8
7
6
5
4
3
2
1
0
DEF DEFERRED TRANSMISSION
Indicates that the SONIC-T has deferred its transmission during the first attempt If subsequent collisions occur this
bit is reset This bit is cleared after the TXpkt status field is written in the TDA
NCRS NO CRS
Indicates that Carrier Sense (CRS) was not present during transmission CRS is monitored from the beginning of the
Start of Frame Delimiter to the last byte transmitted The transmission will not be aborted This bit is set at the start
of preamble and is reset if CRS is detected Hence if CRS is never detected throughout the entire transmission of
the packet this bit will remain set
Note NCRS will always remain set in MAC loopback as long as there is no activity on the RX
CRSL CRS LOST
Indicates that CRS has gone low or has not been present during transmission CRS is monitored from the beginning
of the Start of Frame Delimiter to the last byte transmitted The transmission will not be aborted
Note if CRS was never present both NCRS and CRSL will be set simultaneously Also CRSL will always be set in MAC loopback
EXC EXCESSIVE COLLISIONS
Indicates that 16 collisions have occurred The transmission is aborted
OWC OUT OF WINDOW COLLISION
Indicates that an illegal collision has occurred after 51 2 s (one slot time) from either the first bit of preamble or
from SFD depending upon the POWC bit The transmission backs off as in a normal transmission This bit is cleared
after the TXpkt status field is written in the TDA
Must be 0
PMB PACKET MONITORED BAD
This bit is set if after the receive unit has monitored the transmitted packet the CRC has been calculated as invalid
as a result of a Frame Alignment error or the Source Address does not match any of the CAM address registers
Note 1 The SONIC-T’s CRC checker is active during transmission
Note 2 If CRC has been inhibited for transmissions (CRCI is set) this bit will always be low This is true regardless of Frame Alignment or Source
Address mismatch errors
Note 3 If a Receive FIFO overrun has occurred the transmitted packet is not monitored completely Thus if PMB is set along with the RFO bit in the
ISR then PMB has no meaning The packet must be completely received before PMB has meaning
Note 4 This bit is always zero in loopback mode (True for all three types of looback mode )
FU FIFO UNDERRUN
Indicates that the SONIC-T has not been able to access the bus before the FIFO has emptied This condition occurs
from excessive bus latency and or slow bus clock The transmission is aborted (See Section 3 5 2 )
BCM BYTE COUNT MISMATCH
This bit is set when the SONIC-T detects that the TXpkt pkt size field is not equal to the sum of the
TXpkt frag size field(s) Transmission is aborted This bit will also be set when Excessive Collisions (bit 6 of the
transmit control register) occur during transmission
PTX PACKET TRANSMITTED OK
Indicates that a packet has been transmitted without the following errors
Excessive Collisions (EXC)
Excessive Deferral (EXD)
FIFO Underrun (FU)
Byte Count Mismatch (BCM)
(Continued)
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Description
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