UJA1023T/2R04/C;51 NXP Semiconductors, UJA1023T/2R04/C;51 Datasheet - Page 34
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UJA1023T/2R04/C;51
Manufacturer Part Number
UJA1023T/2R04/C;51
Description
UJA1023T/SO16/TUBEDP//2R04/C
Manufacturer
NXP Semiconductors
Datasheet
1.UJA1023T2R04C51.pdf
(49 pages)
Specifications of UJA1023T/2R04/C;51
Applications
LIN Controller
Interface
SPI
Voltage - Supply
6.5 V ~ 27 V
Package / Case
16-SOIC (3.9mm Width)
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935285403512
Available stocks
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Part Number
Manufacturer
Quantity
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NXP Semiconductors
UJA1023
Product data sheet
7.4 Configuration pins C1 to C3
7.5 LIN transceiver
The structure of the configuration pins C1 to C3 (Cx) is shown in
a pull-up to the battery. The pull-up is switched on during node address configuration only.
In all other cases the Cx have high-impedance behavior.
In order to have a safety margin against ground shift the input threshold of the
configuration pins is about 0.5 × V
In addition the configuration pin C3 has a low-side driver to provide the output signal
during daisy chain ID configuration.
The integrated LIN transceiver of the UJA1023 is compliant with LIN 2.0 / SAE J2602 and
provides:
Fig 11. INH structure
Fig 12. Configuration pin structure
•
•
•
Integrated 30 kΩ termination resistor
Internal LIN-termination switch (RTLIN)
Disabling of termination switch during a short-circuit from LIN to GND
All information provided in this document is subject to legal disclaimers.
ADC mode
output
Rev. 5 — 17 August 2010
FF
FF
Cx
BAT
.
V
0.5V
BAT
configuration on/off
BAT
&
&
&
VIO
Cx input
Cx output
001aad492
R
R
on(INH2)
on(INH2)
BAT
R on(INH1)
Figure
INH
mdb499
UJA1023
© NXP B.V. 2010. All rights reserved.
12. Each pin has
LIN-I/O slave
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