STM32F100VDT6BTR STMicroelectronics, STM32F100VDT6BTR Datasheet - Page 67
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STM32F100VDT6BTR
Manufacturer Part Number
STM32F100VDT6BTR
Description
16/32-BITS MICROS
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet
1.STM32F100RCT6TR.pdf
(97 pages)
Specifications of STM32F100VDT6BTR
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
24MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
80
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM32F100VDT6BTR
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
STM32F100VDT6BTR
Manufacturer:
ST
Quantity:
20 000
STM32F100xC, STM32F100xD, STM32F100xE
5.3.12
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device is monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 39.
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 40.
1. Based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
●
●
These tests are compliant with EIA/JESD78 IC latch-up standard.
Table 41.
Symbol Parameter
V
V
Symbol
Symbol
S
ESD(HBM)
ESD(CDM)
EMI
LU
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
Peak level
Static latch-up class
Electrostatic discharge
voltage (human body model)
Electrostatic discharge
voltage (charge device model)
EMI characteristics
ESD absolute maximum ratings
Electrical sensitivities
Parameter
V
LQFP144 package
compliant with SAE
J1752/3
Ratings
DD
= 3.6 V, T
Conditions
Doc ID 15081 Rev 5
A
T
A
= 25°C,
= +105 °C conforming to JESD78
T
conforming to JESD22-A114
T
conforming to JESD22-C101
A
A
= +25 °C
= +25 °C
30 MHz to 130 MHz
0.1 MHz to 30 MHz
130 MHz to 1GHz
frequency band
SAE EMI Level
Monitored
Conditions
Conditions
Max vs. [f
Electrical characteristics
Class
8/24 MHz
2
II
16
25
25
4
HSE
Maximum
value
/f
HCLK
2000
500
II level A
Class
(1)
]
dBµV
Unit
67/97
Unit
-
V