SST89V58RD2-33-I-TQJE Microchip Technology, SST89V58RD2-33-I-TQJE Datasheet - Page 44

• Manufacturer Part Number: SST89V58RD2-33-I-TQJE
• Description: 2.7V To 3.6V FlashFlex 8-bit 8051 Microcontroller 44 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: FlashFlex®r

Specifications of SST89V58RD2-33-I-TQJE

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP
• Processor Series: FlashFlex51
• Core: C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Data Sheet
7.0 WATCHDOG TIMER
The device offers a programmable Watchdog Timer (WDT)
for fail safe protection against software deadlock and auto-
matic recovery.
To protect the system against software deadlock, the user
software must refresh the WDT within a user-defined time
period. If the software fails to do this periodical refresh, an
internal hardware reset will be initiated if enabled (WDRE=
1). The software can be designed such that the WDT times
out if the program does not work properly.
The WDT in the device uses the system clock (XTAL1) as
its time base. So strictly speaking, it is a watchdog counter
rather than a watchdog timer. The WDT register will incre-
ment every 344,064 crystal clocks. The upper 8-bits of the
time base register (WDTD) are used as the reload register
of the WDT.
©2007 Silicon Storage Technology, Inc.
FIGURE
Ext. RST
CLK (XTAL1)
7-1: Block Diagram of Programmable Watchdog Timer
WDTC
Counter
344064
clks
WDT Upper Byte
44
WDTD
The WDTS flag bit is set by WDT overflow and is not
changed by WDT reset. User software can clear WDTS by
writing “1” to it.
Figure 7-1 provides a block diagram of the WDT. Two SFRs
(WDTC and WDTD) control watchdog timer operation.
During idle mode, WDT operation is temporarily sus-
pended, and resumes upon an interrupt exit from idle.
The time-out period of the WDT is calculated as follows:
where WDTD is the value loaded into the WDTD register
and f
SST89V54RD2/RD / SST89V58RD2/RD
OSC
Period = (255 - WDTD) * 344064 * 1/f
is the oscillator frequency.
WDT Reset
FlashFlex MCU
1255 F22.0
Internal Reset
S71255-10-000
CLK (XTAL1)
12/07