S29PL064J70BFI120 Spansion Inc., S29PL064J70BFI120 Datasheet - Page 69

• Manufacturer Part Number: S29PL064J70BFI120
• Description: Flash Memory
• Manufacturer: Spansion Inc.

16.4
16.5
16.6
December 18, 2009 S29PL-J_00_A12
DQ2: Toggle Bit II
Reading Toggle Bits DQ6/DQ2
DQ5: Exceeded Timing Limits
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that
is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is
valid after the rising edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure.
(The system may use either OE# or CE# (CE1# / CE2# for PL129J) to control the read cycles.) But DQ2
cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison,
indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors
are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to
Table 16.1 on page 70
Figure 16.2 on page 68
on page 69
shows the toggle bit timing diagram.
in graphical form.
Refer to
toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling.
Typically, the system would note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling,
the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on
the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or
erase operation. If it is still toggling, the device did not completed the operation successfully, and the system
must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algorithm when it returns to
determine the status of the operation (top of
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully
completed.
The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously
programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.”
Under both these conditions, the system must write the reset command to return to the read mode (or to the
erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).
Figure 16.2 on page 68
explains the algorithm. See also the
to compare outputs for DQ2 and DQ6.
shows the toggle bit algorithm in flowchart form, and the
D a t a
for the following discussion. Whenever the system initially begins reading
S h e e t
Figure 20.12 on page 82
S29PL-J
Figure 16.2 on page
DQ6: Toggle Bit I on page
shows the differences between DQ2 and DQ6
68).
67.
Figure 20.11 on page 82
DQ2: Toggle Bit II
69