PIC32MX564F128HT-I/MR Microchip Technology, PIC32MX564F128HT-I/MR Datasheet - Page 60
![64 PINS, 128KB Flash, 32KB RAM, 80 MHz, USB, CAN, 4 DMA 64 QFN 9x9x0.9mm T/R](/photos/12/13/121325/c04-149_mr_sml.jpg)
PIC32MX564F128HT-I/MR
Manufacturer Part Number
PIC32MX564F128HT-I/MR
Description
64 PINS, 128KB Flash, 32KB RAM, 80 MHz, USB, CAN, 4 DMA 64 QFN 9x9x0.9mm T/R
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.PIC32MX575F256H-80IMR.pdf
(254 pages)
Specifications of PIC32MX564F128HT-I/MR
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN Exposed Pad
Processor Series
PIC32MX5x
Core
MIPS32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
53
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- Current page: 60 of 254
- Download datasheet (6Mb)
TABLE 4-2:
Legend:
Note 1:
10B0
10C0
10D0
10E0
10F0
1100
1110
1120
1130
1140
1150
IPC10
IPC11
IPC12
2:
IPC2
IPC3
IPC4
IPC5
IPC6
IPC7
IPC8
IPC9
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See
information.
These bits are not available on PIC32MX534/564/664/764 devices.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
INTERRUPT REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H AND
PIC32MX575F512H DEVICES
31/15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30/14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
29/13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
28/12
—
—
—
DMA7IP<2:0>
DMA5IP<2:0>
(1)
CMP1IP<2:0>
RTCCIP<2:0>
DMA3IP<2:0>
DMA1IP<2:0>
INT2IP<2:0>
INT3IP<2:0>
INT4IP<2:0>
I2C1IP<2:0>
SPI2IP<2:0>
I2C4IP<2:0>
AD1IP<2:0>
USBIP<2:0>
IC2IP<2:0>
IC3IP<2:0>
IC4IP<2:0>
IC5IP<2:0>
U3IP<2:0>
U5IP<2:0>
U4IP<2:0>
(CONTINUED)
27/11
—
—
—
(2)
(2)
26/10
—
—
—
DMA7IS<1:0>
DMA5IS<1:0>
25/9
CMP1IS<1:0>
RTCCIS<1:0>
DMA3IS<1:0>
DMA1IS<1:0>
—
—
—
INT2IS<1:0>
INT3IS<1:0>
INT4IS<1:0>
I2C1IS<1:0>
SPI2IS<1:0>
I2C4IS<1:0>
AD1IS<1:0>
USBIS<1:0>
IC2IS<1:0>
IC3IS<1:0>
IC4IS<1:0>
IC5IS<1:0>
U3IS<1:0>
U5IS<1:0>
U4IS<1:0>
24/8
—
—
—
(2)
(2)
Bits
23/7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
22/6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
21/5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
20/4
—
Section 12.1.1 “CLR, SET and INV Registers”
DMA6IP<2:0>
DMA4IP<2:0>
FSCMIP<2:0>
CMP2IP<2:0>
DMA2IP<2:0>
DMA0IP<2:0>
CAN1IP<2:0>
SPI3IP<2:0>
PMPIP<2:0>
SPI4IP<2:0>
OC2IP<2:0>
OC3IP<2:0>
OC4IP<2:0>
OC5IP<2:0>
I2C3IP<2:0>
I2C5IP<2:0>
FCEIP<2:0>
CNIP<2:0>
U1IP<2:0>
U2IP<2:0>
U6IP<2:0>
T2IP<2:0>
T3IP<2:0>
T4IP<2:0>
T5IP<2:0>
19/3
—
(2)
(2)
18/2
—
DMA6IS<1:0>
DMA4IS<1:0>
17/1
CMP2IS<1:0>
FSCMIS<1:0>
DMA2IS<1:0>
DMA0IS<1:0>
CAN1IS<1:0>
OC2IS<1:0>
OC3IS<1:0>
OC4IS<1:0>
OC5IS<1:0>
SPI3IS<1:0>
I2C3IS<1:0>
PMPIS<1:0>
SPI4IS<1:0>
I2C5IS<1:0>
FCEIS<1:0>
—
CNIS<1:0>
U1IS<1:0>
U2IS<1:0>
U6IS<1:0>
T2IS<1:0>
T3IS<1:0>
T4IS<1:0>
T5IS<1:0>
16/0
—
(2)
(2)
for more
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
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