PIC32MX534F064H-I/PT Microchip Technology, PIC32MX534F064H-I/PT Datasheet - Page 49
![64 PINS, 64KB Flash,16KB RAM, 80 MHz, USB, CAN, 4 DMA 64 TQFP 10x10x1mm TRAY](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC32MX534F064H-I/PT
Manufacturer Part Number
PIC32MX534F064H-I/PT
Description
64 PINS, 64KB Flash,16KB RAM, 80 MHz, USB, CAN, 4 DMA 64 TQFP 10x10x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.PIC32MX575F256H-80IMR.pdf
(254 pages)
Specifications of PIC32MX534F064H-I/PT
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Processor Series
PIC32MX5x
Core
MIPS32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
53
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX534F064H-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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Coprocessor 0 also contains the logic for identifying
and managing exceptions. Exceptions can be caused
by a variety of sources, including alignment errors in
data, external events or program errors.
the exception types in order of priority.
TABLE 3-3:
© 2010 Microchip Technology Inc.
Reset
DSS
DINT
NMI
Interrupt
DIB
AdEL
IBE
DBp
Sys
Bp
RI
CpU
CEU
Ov
Tr
DDBL/DDBS
AdEL
AdES
DBE
DDBL
Exception
Assertion MCLR or a Power-on Reset (POR).
EJTAG debug single step.
EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the
EjtagBrk bit in the ECR register.
Assertion of NMI signal.
Assertion of unmasked hardware or software interrupt signal.
EJTAG debug hardware instruction break matched.
Fetch address alignment error.
Fetch reference to protected address.
Instruction fetch bus error.
EJTAG breakpoint (execution of SDBBP instruction).
Execution of SYSCALL instruction.
Execution of BREAK instruction.
Execution of a reserved instruction.
Execution of a coprocessor instruction for a coprocessor that is not enabled.
Execution of a CorExtend instruction when CorExtend is not enabled.
Execution of an arithmetic instruction that overflowed.
Execution of a trap (when trap condition is true).
EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value).
Load address alignment error.
Load reference to protected address.
Store address alignment error.
Store to protected address.
Load or store bus error.
EJTAG data hardware breakpoint matched in load data compare.
PIC32MX5XX/6XX/7XX FAMILY CORE EXCEPTION TYPES
Table 3-3
lists
Description
PIC32MX5XX/6XX/7XX
DS61156F-page 49
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