PIC32MX534F064H-I/PT Microchip Technology, PIC32MX534F064H-I/PT Datasheet - Page 125
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PIC32MX534F064H-I/PT
Manufacturer Part Number
PIC32MX534F064H-I/PT
Description
64 PINS, 64KB Flash,16KB RAM, 80 MHz, USB, CAN, 4 DMA 64 TQFP 10x10x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.PIC32MX575F256H-80IMR.pdf
(254 pages)
Specifications of PIC32MX534F064H-I/PT
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Processor Series
PIC32MX5x
Core
MIPS32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
53
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX534F064H-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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10.0
The PIC32 Direct Memory Access (DMA) controller is a
bus master module useful for data transfers between
different devices without CPU intervention. The source
and destination of a DMA transfer can be any of the
memory mapped modules existent in the PIC32 (such
as Peripheral Bus (PBUS) devices: SPI, UART, PMP,
etc.) or memory itself.
Following are some of the key features of the DMA
controller module:
• Four identical channels, each featuring:
FIGURE 10-1:
© 2010 Microchip Technology Inc.
- Auto-increment source and destination
- Source and destination pointers
- Memory to memory and memory to
INT Controller
Note 1: This data sheet summarizes the features
address registers
peripheral transfers
Peripheral Bus
2: Some registers and associated bits
DIRECT MEMORY ACCESS
(DMA) CONTROLLER
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 31. “Direct
Memory Access (DMA) Controller”
(DS61117)
Reference Manual” , which is available
from
(www.microchip.com/PIC32).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
the
Address Decoder
Global Control
DMA BLOCK DIAGRAM
(DMACON)
in
Microchip
the
System IRQ
“PIC32
web
Family
Channel n Control
Channel 0 Control
Channel 1 Control
site
in
• Automatic word-size detection:
• Fixed priority channel arbitration
• Flexible DMA channel operating modes:
• Flexible DMA requests:
• Multiple DMA channel status interrupts:
• DMA debug support features:
• CRC Generation module:
Channel Priority
PIC32MX5XX/6XX/7XX
- Transfer granularity, down to byte level
- Bytes need not be word-aligned at source
- Manual (software) or automatic (interrupt)
- One-Shot or Auto-Repeat Block Transfer
- Channel-to-channel chaining
- A DMA request can be selected from any of
- Each channel can select any (appropriate)
- A DMA transfer abort can be selected from
- Pattern (data) match transfer termination
- DMA channel block transfer complete
- Source empty or half empty
- Destination full or half full
- DMA transfer aborted due to an external
- Invalid DMA address generated
- Most recent address accessed by a DMA
- Most recent DMA channel to transfer data
- CRC module can be assigned to any of the
- CRC module is highly configurable
Arbitration
I
I
I
I
and destination
DMA requests
modes
the peripheral interrupt sources
observable interrupt as its DMA request
source
any of the peripheral interrupt sources
event
channel
available channels
0
1
2
n
Y
Bus Interface
Device Bus + Bus Arbitration
DS61156F-page 125
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