PIC32MX320F128LT-80I/BG Microchip Technology, PIC32MX320F128LT-80I/BG Datasheet - Page 10

• Manufacturer Part Number: PIC32MX320F128LT-80I/BG
• Description: 128 KB Flash, 32 KB RAM, 80 MHz, 10-Bit ADC 121 XBGA 10x10x1.20mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX320F128LT-80I/BG

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Processor Series: PIC32MX3xx
• Core: MIPS
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC32MX3XX/4XX
21. Module: Input Capture
22. Module: USB
DS80440D-page 10
16-bit DMA transfers from the ICAP module FIFO
buffer do not advance the ICAP FIFO pointer. This
results in the entire DMA output buffer being filled
with the first value from the ICAP FIFO.
Work around
Configure the DMA to perform 32-bit transfers
from the ICAP FIFO.
Affected Silicon Revisions
The USB module does not correctly switch from
full-speed to low-speed after sending a PRE
packet to a hub.
Work around
Connect a low-speed device directly to the PIC32.
Affected Silicon Revisions
B2
B2
X
X
B3
B3
X
X
B4
B4
X
X
B6
B6
X
X
23. Module: DMA
24. Module: PMP
The DMA buffer may be erroneously filled with the
last data read prior to the breakpoint. This buffer fill
will continue until the DMA buffer is full. However,
the DMA buffer fills correctly if those same
peripherals are used as DMA destinations, even
when the CPU goes into Debug Exception mode.
This behavior occurs when the DMA controller is
actively transferring data and a debugger hits a
breakpoint, causes a single-step operation, or
halts the target.
Refer to
input registers that could affect DMA buffer usage.
TABLE 3: REGISTERS AND
Work around
If the debugger halts during a DMA transfer from
one of these registers, either ignore the DMA
transferred data or restart the debug session.
Affected Silicon Revisions
Events can be missed if the PMDIN register is
used as the DMA source or destination and the
PMP IRQ is used as the DMA trigger.
Work around
Do not use DMA for PMP read or write operations.
Affected Silicon Revisions
B2
B2
X
X
Peripheral as DMA
Change Notice
Input Capture
B3
B3
X
X
Source
Table
UART
PMP
SPI
PERIPHERALS AFFECTED BY
BREAKPOINTS DURING DMA
TRANSFERS
B4
B4
X
X
3, which lists the peripherals and
© 2010 Microchip Technology Inc.
B6
B6
X
X
Input Register
Transfer from
UxRXREG
SPIxBUF
ICxBUF
PORTx
PMDIN