PIC24HJ64GP204T-I/PT Microchip Technology, PIC24HJ64GP204T-I/PT Datasheet - Page 108
![16-bit MCU, 64KB Flash,DMA,40 MIPS,nanoWatt 44 TQFP 10x10x1mm T/R](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC24HJ64GP204T-I/PT
Manufacturer Part Number
PIC24HJ64GP204T-I/PT
Description
16-bit MCU, 64KB Flash,DMA,40 MIPS,nanoWatt 44 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP302-ISO.pdf
(368 pages)
3.PIC24HJ32GP302-ISO.pdf
(8 pages)
4.PIC24HJ32GP302-ISO.pdf
(12 pages)
Specifications of PIC24HJ64GP204T-I/PT
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
64KB (22K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC24HJ64GP204T-I/PTTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24HJ64GP204T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC24HJ12GP201-ISO PDF datasheet
- PIC24HJ32GP302-ISO PDF datasheet #2
- PIC24HJ32GP302-ISO PDF datasheet #3
- PIC24HJ32GP302-ISO PDF datasheet #4
- Current page: 108 of 368
- Download datasheet (5Mb)
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04
REGISTER 8-1:
DS70293E-page 108
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10-6
bit 5-4
bit 3-2
bit 1-0
R/W-0
CHEN
U-0
—
CHEN: Channel Enable bit
1 = Channel enabled
0 = Channel disabled
SIZE: Data Transfer Size bit
1 = Byte
0 = Word
DIR: Transfer Direction bit (source/destination bus select)
1 = Read from DMA RAM address, write to peripheral address
0 = Read from peripheral address, write to DMA RAM address
HALF: Early Block Transfer Complete Interrupt Select bit
1 = Initiate block transfer complete interrupt when half of the data has been moved
0 = Initiate block transfer complete interrupt when all of the data has been moved
NULLW: Null Data Peripheral Write Mode Select bit
1 = Null data write to peripheral in addition to DMA RAM write (DIR bit must also be clear)
0 = Normal operation
Unimplemented: Read as ‘0’
AMODE<1:0>: DMA Channel Operating Mode Select bits
11 = Reserved (acts as Peripheral Indirect Addressing mode)
10 = Peripheral Indirect Addressing mode
01 = Register Indirect without Post-Increment mode
00 = Register Indirect with Post-Increment mode
Unimplemented: Read as ‘0’
MODE<1:0>: DMA Channel Operating Mode Select bits
11 = One-Shot, Ping-Pong modes enabled (one block transfer from/to each DMA RAM buffer)
10 = Continuous, Ping-Pong modes enabled
01 = One-Shot, Ping-Pong modes disabled
00 = Continuous, Ping-Pong modes disabled
R/W-0
SIZE
U-0
—
DMAxCON: DMA CHANNEL x CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
DIR
AMODE<1:0>
R/W-0
R/W-0
HALF
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
NULLW
R/W-0
U-0
—
U-0
U-0
—
—
© 2011 Microchip Technology Inc.
x = Bit is unknown
R/W-0
U-0
—
MODE<1:0>
R/W-0
U-0
—
bit 8
bit 0
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