PIC24HJ16GP304T-I/ML Microchip Technology, PIC24HJ16GP304T-I/ML Datasheet - Page 48
![16-bit MCU, 16KB Flash,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm T/R](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC24HJ16GP304T-I/ML
Manufacturer Part Number
PIC24HJ16GP304T-I/ML
Description
16-bit MCU, 16KB Flash,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm T/R
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP202-ISO.pdf
(272 pages)
3.PIC24HJ32GP202-ISO.pdf
(8 pages)
4.PIC24HJ32GP202-ISO.pdf
(12 pages)
Specifications of PIC24HJ16GP304T-I/ML
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (5.5K x 24)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC24HJ16GP304T-I/MLTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24HJ16GP304T-I/ML
Manufacturer:
MICROCHIP
Quantity:
12 000
- PIC24HJ12GP201-ISO PDF datasheet
- PIC24HJ32GP202-ISO PDF datasheet #2
- PIC24HJ32GP202-ISO PDF datasheet #3
- PIC24HJ32GP202-ISO PDF datasheet #4
- Current page: 48 of 272
- Download datasheet (4Mb)
PIC24HJ32GP202/204 AND PIC24HJ16GP304
5.2
The PIC24HJ32GP202/204 and PIC24HJ16GP304
Flash program memory array is organized into rows of
64 instructions or 192 bytes. RTSP allows the user
application to erase a page of memory, which consists
of eight rows (512 instructions) at a time, and to
program one row or one word at a time. The 8-row
erase pages and single row write rows are
edge-aligned from the beginning of program memory,
on boundaries of 1536 bytes and 192 bytes,
respectively.
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers sequentially. The
instruction words loaded must always be from a group
of 64 boundary.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register. A total
of 64 TBLWTL and TBLWTH instructions are required
to load the instructions.
All table write operations are single-word writes (two
instruction cycles) because only the buffers are written.
A programming cycle is required for programming each
row.
5.3
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode.
programming operation is finished.
The programming time depends on the FRC accuracy
(see
Tuning register (see
formula to calculate the minimum and maximum values
for the Row Write Time, Page Erase Time, and Word
Write Cycle Time parameters (see
EQUATION 5-1:
DS70289G-page 48
------------------------------------------------------------------------------------------------------------------------- -
7.37 MHz
Table
The
RTSP Operation
Programming Operations
22-18) and the value of the FRC Oscillator
×
processor
(
FRC Accuracy
Register
PROGRAMMING TIME
T
stalls
)%
8-4). Use the following
×
Table
(
(waits)
FRC Tuning
22-12).
until
)%
the
For example, if the device is operating at +125°C,
the FRC accuracy will be ±5%. If the TUN<5:0> bits
(see
minimum row write time is equal to
EQUATION 5-2:
The maximum row write time is equal to
EQUATION 5-3:
Setting the WR bit (NVMCON<15>) starts the
operaion, and the WR bit is automatically cleared when
the operation is finished.
5.4
The two SFRs that are used to read and write the
program Flash memory are:
•
•
The NVMCON register
blocks need to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY
used for write protection. To start a programming or
erase
consecutively write 0x55 and 0xAA to the NVMKEY
register.
Operations”
T
T
RW
RW
NVMCON: Flash Memory Control Register
NVMKEY: Nonvolatile Memory Key Register
=
=
Register
--------------------------------------------------------------------------------------------- - 1.586ms
7.37 MHz
---------------------------------------------------------------------------------------------- 1.435ms
7.37 MHz
sequence,
Control Registers
(Register
Refer
for further details.
8-4) are set to
×
×
(
to
(
11064 Cycles
11064 Cycles
5-2) is a write-only register that is
1 0.05
1
–
+
the
MINIMUM ROW WRITE
TIME
MAXIMUM ROW WRITE
TIME
© 2011 Microchip Technology Inc.
0.05
Section 5.3
(Register
)
)
user
×
×
(
(
1 0.00375
1 0.00375
–
–
5-1) controls which
Equation
application
‘b111111, the
“Programming
Equation
)
)
=
=
5-2.
must
5-3.
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