PIC24FJ32GA004T-I/PT Microchip Technology, PIC24FJ32GA004T-I/PT Datasheet - Page 12
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PIC24FJ32GA004T-I/PT
Manufacturer Part Number
PIC24FJ32GA004T-I/PT
Description
32KB, Flash, 8192bytes-RAM, 16MIPS, 35I/O, 16-bit Family,nanoWatt 44 TQFP 10x10x
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ16GA002-ISS.pdf
(52 pages)
2.PIC24FJ16GA002-ISS.pdf
(268 pages)
3.PIC24FJ16GA002-ISS.pdf
(22 pages)
Specifications of PIC24FJ32GA004T-I/PT
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (11K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164335 - MODULE SKT FOR 10X10 PM3 44TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC24FJ32GA004T-I/PTTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ32GA004T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC24FJ32GA004T-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC24FJ64GA004 FAMILY
30. Module: UART (FIFO Error Flags)
31. Module: Core (BOR)
DS80470E-page 12
Under certain circumstances, the PERR and
FERR error bits may not be correct for all bytes in
the receive FIFO. This has only been observed
when both of the following conditions are met:
• the UART receive interrupt is set to occur when
• more than 2 bytes with an error are received.
In these cases, only the first two bytes, with a
parity or framing error, will have the corresponding
bits indicate correctly. The error bits will not be set
after this.
Work around
None.
Affected Silicon Revisions
When the on-chip regulator is enabled (DISVREG
tied to V
occur under the following circumstances:
• V
• the internal band gap reference is being used as
Work around
Do not select the internal band gap as a reference
for the A/D converter when the on-chip regulator is
in Tracking mode (LVDIF (IFS4<8>) = 1).
Affected Silicon Revisions
A3/
A3/
A4
A4
the FIFO is full or 3/4 full (UxSTA<7:6> = 1x),
and
X
a reference with the A/D converter
(AD1PCFG<15> = 0)
X
DD
is less than 2.5V, and
B4
B4
X
X
SS
), a BOR event may spontaneously
B5
B5
X
X
B8
B8
X
X
32. Module: Core (Instruction Set)
33. Module: Memory (Program Space
If an instruction producing a read-after-write stall
condition is executed inside a REPEAT loop, the
instruction will be executed fewer times than was
intended. For example, this loop:
repeat #0xf
inc [w1],[++w1]
will execute less than 16 times.
Work around
Avoid using REPEAT to repetitively execute
instructions that create a stall condition. Instead,
use a software loop using conditional branches.
The MPLAB
REPEAT loops that cause this erratum.
Affected Silicon Revisions
When accessing data in the PSV area of data
RAM, it is possible to generate a false address
error trap condition by reading data located
precisely at the lower address boundary (8000h).
If data is read using an instruction with an auto-
decrement, the resulting RAM address will be
below the PSV boundary (i.e., at 7FFEh); this will
result in an address error trap.
This false address error can also occur if a 32-bit
MOV instruction is used to read the data at location,
8000h.
Work around
Do not use the first location of the a PSV page
(address 8000h).
The MPLAB C Compiler (v3.11 or later) supports
the option, -merrata=psv_trap, to prevent it
from generating code that would cause this
erratum.
Affected Silicon Revisions
A3/
A3/
A4
A4
X
X
B4
B4
X
Visibility)
®
B5
B5
X
C Compiler will not generate
2010 Microchip Technology Inc.
B8
B8