PIC24FJ128DA110T-I/BG Microchip Technology, PIC24FJ128DA110T-I/BG Datasheet - Page 72
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PIC24FJ128DA110T-I/BG
Manufacturer Part Number
PIC24FJ128DA110T-I/BG
Description
16-bit, 128KB Flash, 24K RAM, USB, Graphics 121 XBGA 10x10x1.20mm T/R
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Specifications of PIC24FJ128DA110T-I/BG
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, GFX, LVD, POR, PWM, WDT
Number Of I /o
84
Program Memory Size
128KB (43K x 24)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
121-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ128DA110T-I/BG
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC24FJ256DA210 FAMILY
4.2.5.1
In order to read the data from the EDS space, first, an
Address Pointer is set up by loading the required EDS
page number into the DSRPAG register and assigning
the offset address to one of the W registers. Once the
above assignment is done, the EDS window is enabled
FIGURE 4-5:
When the Most Significant bit (MSBs) of EA is ‘1’ and
DSRPAG<9> = 0, the lower 9 bits of DSRPAG are con-
catenated to the lower 15 bits of EA to form a 24-bit
EDS space address for read operations.
Example 4-1 shows how to read a byte, word and
double-word from EDS.
EXAMPLE 4-1:
DS39969B-page 72
; Set the EDS page from where the data to be read
bset
;Read a byte from the selected location
;Read a word from the selected location
;Read Double - word from the selected location
mov
mov
mov
mov.b
mov.b
mov
mov.d
Data Read from EDS Space
w1 , #15
#0x0002 , w0
w0 , DSRPAG
#0x0800 ,
[w1++] ,
[w1++] , w3
[w1] , w2
[w1] , w2
9
EDS ADDRESS GENERATION FOR READ OPERATIONS
0 = Extended SRAM and EPMP
EDS READ CODE IN ASSEMBLY
8
DSRPAG Reg
9 Bits
w1
;set the MSB of the base address, enable EDS mode
w2
Select
;page 2 is selected for read
;select the location (0x800) to be read
;read Low byte
;read High byte
;
;two word read, stored in w2 and w3
0
1
24-Bit EA
Wn
by setting bit 15 of the working register, assigned with
the offset address; then, the contents of the pointed
EDS location can be read.
Figure 4-5 illustrates how the EDS space address is
generated for read operations.
15 Bits
Note:
All read operations from EDS space have
an overhead of one instruction cycle.
Therefore, a minimum of two instruction
cycles is required to complete an EDS
read. EDS reads under the REPEAT
instruction; the first two accesses take
three
accesses take one cycle.
Wn<0> is Byte Select
cycles
2010 Microchip Technology Inc.
and
the
subsequent
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