PIC24F04KA200T-I/ST Microchip Technology, PIC24F04KA200T-I/ST Datasheet - Page 4

• Manufacturer Part Number: PIC24F04KA200T-I/ST
• Description: PIC24F Core, 4KB Flash, 512B RAM, 3V, Deep Sleep, 10-bit 500ksps ADC, CTMU, UART
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F04KA200T-I/ST

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 4KB (1.375K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC24F04KA201 FAMILY
4. Module: SPI (Enhanced Buffer Mode)
5. Module: Core (Low-Power BOR)
DS80474B-page 4
In Enhanced Buffer mode (SPI1CON2<0> = 1),
polling the SPI Transmit Buffer Full bit, SPITBF
(SPI1STAT<1>), may produce erroneous results.
This occurs only under two circumstances:
•
•
For Master mode, this includes all combinations
of the primary prescale bits (SPI11CON1<1:0>)
and secondary prescale bits (SPI1CON1<4:2>)
that, when combined, create an SPI sample
clock divisor with a value of four or greater.
Work around
Instead of polling the SPITBF bit to test for an
empty buffer (SPI1STAT<1> = 0), implement a
SPI receive interrupt handler in software and
add to the SPI transmit buffer in this routine.
Alternatively, poll the SPI Receive Full bit,
SPIRBF (SPI1STAT<0>), or the Shift Register
Empty bit, SRMPT (SPI1STAT<7>), to determine
when to service the SPI transmit and transmit
buffers.
Affected Silicon Revisions
When
(FPOR<6:5> = 00), Brown-out Reset events
may result in a device Reset in which both the
BOR and POR bits are set.
This differs from the expected behavior of simply
re-arming the POR circuit to ensure that a
Power-on Reset occurs when V
the POR threshold.
Work around
None.
Affected Silicon Revisions
A1
A1
X
X
In Master mode, when the SPI divide clock
is 4 or greater.
In Slave mode, when the SPI sample clock
is slower than 1/4 of the CPU instruction
time (T
the
CY
).
low-power
BOR
DD
is
drops below
enabled
6. Module: Comparator (I/O Pins)
7. Module: Comparator
Certain I/O pins may not function correctly as
digital inputs or outputs after specific comparator
outputs have been enabled with the COE bit
(CMxCON<14> = 1). These are:
•
•
This condition may continue, even after the com-
parator in question has been disabled using the
corresponding CON bit (CMxCON<15> = 0).
Work around
In addition to clearing the CON bit, also clear the
COE bit.
Affected Silicon Revisions
When a comparator is programmed to trig-
ger
(CMxCON<7:6> = 10 or 01), setting the CPOL bit
(CMxCON<13> = 1) may cause the comparator to
flag the opposite edge-detect event (e.g., a
high-to-low edge instead of the programmed
low-to-high).
Work around
Leave CPOL = 0. In addition, use the opposite
setting of CMxCON<7:6> to achieve the correct
response (e.g., use ‘10’ for ‘01’).
Affected Silicon Revisions
A1
A1
X
X
RB14 (with Comparator 1)
RA6 (with Comparator 2)
on
certain
 2011 Microchip Technology Inc.
edge-detect
events